> Atomic operations are undefined behavior on ARM for device or strongly
> ordered memory types. So use write-combine variants for mappings. This
> corresponds to normal, non-cacheable memory on ARM. For many other
> architectures, this change should not change the mapping type.
Hi, all
I have
Atomic operations are undefined behavior on ARM for device or strongly
ordered memory types. So use write-combine variants for mappings. This
corresponds to normal, non-cacheable memory on ARM. For many other
architectures, this change should not change the mapping type.
Hi, all
I have met
On Tue, Apr 09, 2013 at 08:53:18PM -0700, Colin Cross wrote:
> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
> > - return ioremap(start, size);
> > + return ioremap_wc(start, size);
>
> ioremap_wc corresponds to MT_DEVICE_WC, which is still device memory,
> so I don't see how
On Tue, Apr 09, 2013 at 08:53:18PM -0700, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring robherri...@gmail.com wrote:
- return ioremap(start, size);
+ return ioremap_wc(start, size);
ioremap_wc corresponds to MT_DEVICE_WC, which is still device memory,
so I
On Tue, Apr 16, 2013 at 01:58:27PM +0100, Rob Herring wrote:
> On 04/16/2013 03:44 AM, Will Deacon wrote:
> > On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
> >> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring wrote:
> >>> Exclusive accesses still have further restrictions. From
On 04/16/2013 03:44 AM, Will Deacon wrote:
> On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
>> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring wrote:
>>> Exclusive accesses still have further restrictions. From section 3.4.5:
>>>
>>> • It is IMPLEMENTATION DEFINED whether LDREX and
On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
> On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring wrote:
> > Exclusive accesses still have further restrictions. From section 3.4.5:
> >
> > • It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be
> > performed to a memory
On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring robherri...@gmail.com wrote:
Exclusive accesses still have further restrictions. From section 3.4.5:
• It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be
performed
On 04/16/2013 03:44 AM, Will Deacon wrote:
On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring robherri...@gmail.com wrote:
Exclusive accesses still have further restrictions. From section 3.4.5:
• It is IMPLEMENTATION DEFINED whether
On Tue, Apr 16, 2013 at 01:58:27PM +0100, Rob Herring wrote:
On 04/16/2013 03:44 AM, Will Deacon wrote:
On Tue, Apr 16, 2013 at 01:43:09AM +0100, Colin Cross wrote:
On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring robherri...@gmail.com wrote:
Exclusive accesses still have further restrictions.
On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring wrote:
> On 04/15/2013 05:21 PM, Colin Cross wrote:
>> On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring wrote:
>>> On 04/09/2013 10:53 PM, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
> From: Rob Herring
>
>
On 04/15/2013 05:21 PM, Colin Cross wrote:
> On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring wrote:
>> On 04/09/2013 10:53 PM, Colin Cross wrote:
>>> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
From: Rob Herring
Atomic operations are undefined behavior on ARM for device or
On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring wrote:
> On 04/09/2013 10:53 PM, Colin Cross wrote:
>> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
>>> From: Rob Herring
>>>
>>> Atomic operations are undefined behavior on ARM for device or strongly
>>> ordered memory types. So use
On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring robherri...@gmail.com wrote:
On 04/09/2013 10:53 PM, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Atomic operations are undefined behavior on ARM for device or
On 04/15/2013 05:21 PM, Colin Cross wrote:
On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring robherri...@gmail.com wrote:
On 04/09/2013 10:53 PM, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Atomic operations
On Mon, Apr 15, 2013 at 4:59 PM, Rob Herring robherri...@gmail.com wrote:
On 04/15/2013 05:21 PM, Colin Cross wrote:
On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring robherri...@gmail.com wrote:
On 04/09/2013 10:53 PM, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring
On 04/09/2013 10:53 PM, Colin Cross wrote:
> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
>> From: Rob Herring
>>
>> Atomic operations are undefined behavior on ARM for device or strongly
>> ordered memory types. So use write-combine variants for mappings. This
>> corresponds to normal,
On 04/09/2013 10:53 PM, Colin Cross wrote:
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Atomic operations are undefined behavior on ARM for device or strongly
ordered memory types. So use write-combine variants for
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring wrote:
> From: Rob Herring
>
> Atomic operations are undefined behavior on ARM for device or strongly
> ordered memory types. So use write-combine variants for mappings. This
> corresponds to normal, non-cacheable memory on ARM. For many other
>
From: Rob Herring
Atomic operations are undefined behavior on ARM for device or strongly
ordered memory types. So use write-combine variants for mappings. This
corresponds to normal, non-cacheable memory on ARM. For many other
architectures, this change should not change the mapping type.
From: Rob Herring rob.herr...@calxeda.com
Atomic operations are undefined behavior on ARM for device or strongly
ordered memory types. So use write-combine variants for mappings. This
corresponds to normal, non-cacheable memory on ARM. For many other
architectures, this change should not change
On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Atomic operations are undefined behavior on ARM for device or strongly
ordered memory types. So use write-combine variants for mappings. This
corresponds to normal, non-cacheable
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