Hi GVRao,
Thank you for pinging me privately.
On Mon, Jun 22, 2020 at 02:19:22PM +, Venkateshwar Rao Gannavarapu wrote:
> On Wednesday, June 17, 2020 3:18 AM, Laurent Pinchart wrote:
> > On Tue, Jun 09, 2020 at 02:48:25AM +, Venkateshwar Rao Gannavarapu
> > wrote:
> >> Hi Laurent,
> >>
>
rg; Sandip Kothari
>; Vishal Sagar
>Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
>
>Hi GVRao,
>
>Sorry for the delayed reply.
>
>On Tue, Jun 09, 2020 at 02:48:25AM +, Venkateshwar Rao Gannavarapu
>wrote:
>> Hi Laurent,
>>
>&g
Hi GVRao,
Sorry for the delayed reply.
On Tue, Jun 09, 2020 at 02:48:25AM +, Venkateshwar Rao Gannavarapu wrote:
> Hi Laurent,
>
> Thanks for the review.
> Please see my comments about D-PHY and bridge driver implementation.
>
> On Sunday, June 7, 2020 7:55 AM, Laurent Pinchart wrote:
> >
t;airl...@linux.ie; dan...@ffwll.ch; linux-kernel@vger.kernel.org; Sandip Kothari
>
>Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
>
>Hi GVRao,
>
>On Sun, May 31, 2020 at 05:41:50PM +, Venkateshwar Rao Gannavarapu
>wrote:
>> On Sunday,
Hi GVRao,
On Sun, May 31, 2020 at 05:41:50PM +, Venkateshwar Rao Gannavarapu wrote:
> On Sunday, May 24, 2020 8:38 AM, Laurent Pinchart wrote:
> > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> >>> The
gt;ker...@vger.kernel.org; Sandip Kothari ; Venkateshwar
>Rao Gannavarapu
>Subject: Re: [RFC PATCH 2/2] drm: xlnx: driver for Xilinx DSI TX Subsystem
>
>Hi GVRao,
>
>Thank you for the patch.
>
>On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
>> On Mon, 202
Hi Laurent,
On Wed, 2020-05-27 at 15:45:24 -0700, Laurent Pinchart wrote:
> Hi Hyun,
>
> On Wed, May 27, 2020 at 10:54:35AM -0700, Hyun Kwon wrote:
> > On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote:
> > > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> > >> On Mon, 202
Hi Hyun,
On Wed, May 27, 2020 at 10:54:35AM -0700, Hyun Kwon wrote:
> On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote:
> > On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> >> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> >>> The Xilinx MIPI DS
Hi Laurent,
On Sat, 2020-05-23 at 20:08:13 -0700, Laurent Pinchart wrote:
> Hi GVRao,
>
> Thank you for the patch.
>
> On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> > On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> > > The Xilinx MIPI DSI Tx Subsystem s
Hi GVRao,
Thank you for the patch.
On Mon, May 04, 2020 at 11:43:48AM -0700, Hyun Kwon wrote:
> On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> > The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
> > data from AXI-4 stream interface.
> >
> > It support
Hi GVRao,
Thanks for the patch. Sorry for late reply.
On Mon, 2020-04-20 at 14:20:56 -0700, Venkateshwar Rao Gannavarapu wrote:
> The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video
> data from AXI-4 stream interface.
>
> It supports upto 4 lanes, optional register interface for th
11 matches
Mail list logo
