On Thu, Jan 21, 2021 at 06:15:06PM +, Marc Zyngier wrote:
> On 2021-01-21 17:55, Will Deacon wrote:
> > On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
> > > On 2021-01-21 15:12, Mohamed Mediouni wrote:
> > > > Please ignore that patch.
> > > >
> > > > It turns out that the PCIe
> On 21 Jan 2021, at 19:15, Marc Zyngier wrote:
>
> On 2021-01-21 17:55, Will Deacon wrote:
>> On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
>>> On 2021-01-21 15:12, Mohamed Mediouni wrote:
Please ignore that patch.
It turns out that the PCIe controller on Apple
On 2021-01-21 17:55, Will Deacon wrote:
On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
On 2021-01-21 15:12, Mohamed Mediouni wrote:
> Please ignore that patch.
>
> It turns out that the PCIe controller on Apple M1 expects posted
> writes and so the memory range for it ought to be
On Thu, Jan 21, 2021 at 04:25:54PM +, Marc Zyngier wrote:
> On 2021-01-21 15:12, Mohamed Mediouni wrote:
> > Please ignore that patch.
> >
> > It turns out that the PCIe controller on Apple M1 expects posted
> > writes and so the memory range for it ought to be set nGnRE.
> > So, we need to
On 2021-01-21 15:12, Mohamed Mediouni wrote:
Please ignore that patch.
It turns out that the PCIe controller on Apple M1 expects posted
writes and so the memory range for it ought to be set nGnRE.
So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.
The MAIR approach isn’t
> On 21 Jan 2021, at 13:47, Will Deacon wrote:
>
> On Thu, Jan 21, 2021 at 11:44:23AM +, Marc Zyngier wrote:
>> On 2021-01-21 11:27, Will Deacon wrote:
>>> On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a
On Thu, Jan 21, 2021 at 11:44:23AM +, Marc Zyngier wrote:
> On 2021-01-21 11:27, Will Deacon wrote:
> > On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
> > > Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious
> > > hardware quirk.
> > >
> > > On Apple
On 2021-01-21 11:27, Will Deacon wrote:
On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious
hardware quirk.
On Apple processors, writes using the nGnRE device memory type get
dropped in flight,
getting to
On Thu, Jan 21, 2021 at 12:32 PM Will Deacon wrote:
> On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
> > Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
> > quirk.
> > /*
> > * Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal
On Wed, Jan 20, 2021 at 02:27:13PM +0100, Mohamed Mediouni wrote:
> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
> quirk.
>
> On Apple processors, writes using the nGnRE device memory type get dropped in
> flight,
> getting to nowhere.
>
> Signed-off-by: Stan
On 20.01.21 19:06, Mohamed Mediouni wrote:
On 20 Jan 2021, at 17:47, Alexander Graf wrote:
On 20.01.21 14:27, Mohamed Mediouni wrote:
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
quirk.
On Apple processors, writes using the nGnRE device memory type get
> On 20 Jan 2021, at 17:47, Alexander Graf wrote:
>
> On 20.01.21 14:27, Mohamed Mediouni wrote:
>> Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
>> quirk.
>> On Apple processors, writes using the nGnRE device memory type get dropped
>> in flight,
>> getting to
On 20.01.21 14:27, Mohamed Mediouni wrote:
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
quirk.
On Apple processors, writes using the nGnRE device memory type get dropped in
flight,
getting to nowhere.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed
Use nGnRnE instead of nGnRE on Apple SoCs to workaround a serious hardware
quirk.
On Apple processors, writes using the nGnRE device memory type get dropped in
flight,
getting to nowhere.
Signed-off-by: Stan Skowronek
Signed-off-by: Mohamed Mediouni
---
arch/arm64/mm/proc.S | 26
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