On Wed, Jun 25, 2014 at 03:06:33PM +0100, Peter Maydell wrote:
> On 25 June 2014 10:28, Marc Zyngier wrote:
> > For this case, the GIC architecture provides EOImode == 1, where:
> > - A write to the EOI register drops the priority of the interrupt and leaves
> > it active. Other interrupts at the
On 06/25/2014 11:28 AM, Marc Zyngier wrote:
> So far, GICv2 has been used in with EOImode == 0. The effect of this
> mode is to perform the priority drop and the deactivation of the
> interrupt at the same time.
>
> While this works perfectly for Linux (we only have a single priority),
> it causes
On 01/07/14 17:34, Stefano Stabellini wrote:
> On Tue, 1 Jul 2014, Marc Zyngier wrote:
>> Hi Stefano,
>>
>> On 30/06/14 20:09, Stefano Stabellini wrote:
>>> On Wed, 25 Jun 2014, Anup Patel wrote:
Hi Marc,
On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
> So far, GICv2 has b
On Tue, 1 Jul 2014, Marc Zyngier wrote:
> Hi Stefano,
>
> On 30/06/14 20:09, Stefano Stabellini wrote:
> > On Wed, 25 Jun 2014, Anup Patel wrote:
> >> Hi Marc,
> >>
> >> On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
> >>> So far, GICv2 has been used in with EOImode == 0. The effect of this
Hi Stefano,
On 30/06/14 20:09, Stefano Stabellini wrote:
> On Wed, 25 Jun 2014, Anup Patel wrote:
>> Hi Marc,
>>
>> On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
>>> So far, GICv2 has been used in with EOImode == 0. The effect of this
>>> mode is to perform the priority drop and the deacti
On Wed, 25 Jun 2014, Anup Patel wrote:
> Hi Marc,
>
> On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
> > So far, GICv2 has been used in with EOImode == 0. The effect of this
> > mode is to perform the priority drop and the deactivation of the
> > interrupt at the same time.
> >
> > While th
+ if (resource_size(&cpu_res) >= SZ_8K)
+ supports_deactivate = true;
+ else
+ pr_warn("GIC: CPU interface size is %x, DT is probably
wrong\n", (int)resource_size(&cpu_res));
This will not work on APM X-Gene because, for
X
On 25/06/14 15:06, Peter Maydell wrote:
> On 25 June 2014 10:28, Marc Zyngier wrote:
>> For this case, the GIC architecture provides EOImode == 1, where:
>> - A write to the EOI register drops the priority of the interrupt and leaves
>> it active. Other interrupts at the same priority level can no
On 25/06/14 15:03, Ian Campbell wrote:
> On Wed, 2014-06-25 at 19:26 +0530, Anup Patel wrote:
>>
>> Ian had send-out a patch long time back to extend
>> GIC dt-bindings for addressing this issue.
>> (http://www.spinics.net/lists/arm-kernel/msg283767.html)
>
> I've been meaning to revisit this. Sin
On Wed, 2014-06-25 at 15:24 +0100, Marc Zyngier wrote:
> > Ian had send-out a patch long time back to extend GIC dt-bindings for
> > addressing this issue.
> > (http://www.spinics.net/lists/arm-kernel/msg283767.html)
>
> Wow. That's really horrible. Blimey! Ian, you owe me a few beers, just
> so
Hi Anup,
On 25/06/14 14:56, Anup Patel wrote:
> Hi Marc,
>
> On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
>> So far, GICv2 has been used in with EOImode == 0. The effect of this
>> mode is to perform the priority drop and the deactivation of the
>> interrupt at the same time.
>>
>> While
On Wed, Jun 25, 2014 at 8:56 AM, Anup Patel wrote:
> Hi Marc,
>
> On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
>> So far, GICv2 has been used in with EOImode == 0. The effect of this
>> mode is to perform the priority drop and the deactivation of the
>> interrupt at the same time.
>>
>> W
On 25 June 2014 10:28, Marc Zyngier wrote:
> For this case, the GIC architecture provides EOImode == 1, where:
> - A write to the EOI register drops the priority of the interrupt and leaves
> it active. Other interrupts at the same priority level can now be taken,
> but the active interrupt cannot
On Wed, 2014-06-25 at 19:26 +0530, Anup Patel wrote:
>
> Ian had send-out a patch long time back to extend
> GIC dt-bindings for addressing this issue.
> (http://www.spinics.net/lists/arm-kernel/msg283767.html)
I've been meaning to revisit this. Since that original patch I've been
wondering if so
Hi Marc,
On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
> So far, GICv2 has been used in with EOImode == 0. The effect of this
> mode is to perform the priority drop and the deactivation of the
> interrupt at the same time.
>
> While this works perfectly for Linux (we only have a single pri
On Wed, Jun 25, 2014 at 8:03 AM, Marc Zyngier wrote:
> On Wed, Jun 25 2014 at 01:50:12 PM, Rob Herring wrote:
>> On Wed, Jun 25, 2014 at 4:28 AM, Marc Zyngier wrote:
>>> So far, GICv2 has been used in with EOImode == 0. The effect of this
>>> mode is to perform the priority drop and the deactiva
On Wed, Jun 25 2014 at 01:50:12 PM, Rob Herring wrote:
> On Wed, Jun 25, 2014 at 4:28 AM, Marc Zyngier wrote:
>> So far, GICv2 has been used in with EOImode == 0. The effect of this
>> mode is to perform the priority drop and the deactivation of the
>> interrupt at the same time.
>>
>> While this
On Wed, Jun 25, 2014 at 4:28 AM, Marc Zyngier wrote:
> So far, GICv2 has been used in with EOImode == 0. The effect of this
> mode is to perform the priority drop and the deactivation of the
> interrupt at the same time.
>
> While this works perfectly for Linux (we only have a single priority),
>
So far, GICv2 has been used in with EOImode == 0. The effect of this
mode is to perform the priority drop and the deactivation of the
interrupt at the same time.
While this works perfectly for Linux (we only have a single priority),
it causes issues when an interrupt is forwarded to a guest, and w
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