Hi Subhash
On 05/17/2018 03:01 AM, Subhash Jadavani wrote:
> On 2018-05-15 21:31, Alim Akhtar wrote:
>> Ping !!!
>>
>> On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar
>> wrote:
>>> Currently DMA mask for UFS HCI is set by reading CAP register's
>>> [64AS] bit. Some HCI controller like Exynos support
On 2018-05-15 21:31, Alim Akhtar wrote:
Ping !!!
On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar
wrote:
Currently DMA mask for UFS HCI is set by reading CAP register's
[64AS] bit. Some HCI controller like Exynos support 36-bit bus
address.
This works perfectly fine with DMA mask set as 64 in ca
Ping !!!
On Thu, Mar 8, 2018 at 4:33 PM, Alim Akhtar wrote:
> Currently DMA mask for UFS HCI is set by reading CAP register's
> [64AS] bit. Some HCI controller like Exynos support 36-bit bus address.
> This works perfectly fine with DMA mask set as 64 in case there is no
> IOMMU attached to HCI.
Currently DMA mask for UFS HCI is set by reading CAP register's
[64AS] bit. Some HCI controller like Exynos support 36-bit bus address.
This works perfectly fine with DMA mask set as 64 in case there is no
IOMMU attached to HCI.
In case if HCI is behind an IOMMU, setting DMA mask as 64 bit won't
wo
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