On 2016/7/22 21:27, Arnd Bergmann wrote:
> On Friday, July 22, 2016 11:56:49 AM CEST Mark Rutland wrote:
>> Hi,
>>
>> I understand that some SoC/socket level PMU is accessed via these
>> registers. It doesn't make sense to review either in isolation. Please
>> put together a unified series, with bo
On 2016/7/22 18:56, Mark Rutland wrote:
> Hi,
>
> I understand that some SoC/socket level PMU is accessed via these
> registers. It doesn't make sense to review either in isolation. Please
> put together a unified series, with both the djtag accessors and the
> PMU code.
>
> On it's own, it's *ve
On Friday, July 22, 2016 11:56:49 AM CEST Mark Rutland wrote:
> Hi,
>
> I understand that some SoC/socket level PMU is accessed via these
> registers. It doesn't make sense to review either in isolation. Please
> put together a unified series, with both the djtag accessors and the
> PMU code.
>
>
Hi,
I understand that some SoC/socket level PMU is accessed via these
registers. It doesn't make sense to review either in isolation. Please
put together a unified series, with both the djtag accessors and the
PMU code.
On it's own, it's *very* difficult to understand how this fits into the
SoC,
Tan Xiaojun (2):
Documentation: arm64: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts
bindings
drivers: soc: Add support for Hisilicon Djtag driver
.../bindings/arm/hisilicon/hisilicon.txt | 98 +
drivers/soc/Kconfig|1 +
drivers/soc/M
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