Since it has been redesigned with new version spec, please change the
first-author :)
And add me as Co-developed.
On Tue, May 26, 2020 at 3:03 PM Greentime Hu wrote:
>
> From: Guo Ren
>
> Follow the riscv vector spec to add new csr number.
>
> [greentime...@sifive.com: update the defined value
On Mon, Jun 1, 2020 at 4:15 PM Greentime Hu wrote:
>
> Guo Ren 於 2020年5月31日 週日 上午9:56寫道:
> >
> > Hi Greentime,
> >
> > Why remove vxrm and xstat ?
> >
> > > Appendix B: Calling Convention
> > > In the RISC-V psABI, the vector registers v0-v31 are all caller-saved.
> > > The vstart, vl, and vtype
Guo Ren 於 2020年5月31日 週日 上午9:56寫道:
>
> Hi Greentime,
>
> Why remove vxrm and xstat ?
>
> > Appendix B: Calling Convention
> > In the RISC-V psABI, the vector registers v0-v31 are all caller-saved. The
> > vstart, vl, and vtype CSRs are also caller-saved.
> > The vxrm and vxsat fields have thread s
Hi Greentime,
Why remove vxrm and xstat ?
> Appendix B: Calling Convention
> In the RISC-V psABI, the vector registers v0-v31 are all caller-saved. The
> vstart, vl, and vtype CSRs are also caller-saved.
> The vxrm and vxsat fields have thread storage duration.
As spec 0.9 mentioned above, vxrm
From: Guo Ren
Follow the riscv vector spec to add new csr number.
[greentime...@sifive.com: update the defined value based on new spec and
remove unused ones]
Signed-off-by: Greentime Hu
Signed-off-by: Guo Ren
---
arch/riscv/include/asm/csr.h | 16 ++--
1 file changed, 14 insertio
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