Jiang,
On Mon, 19 May 2014, Thomas Gleixner wrote:
> > We may build hierarchy irqdomains as below for x86,
> > [IOAPIC] [MSI/MSI-x] [HPET] [DMAR] [Legacy]
> > || | | |
> > vv v | |
> > [ Remapping
Jiang,
On Sun, 18 May 2014, Jiang Liu wrote:
> On 2014/5/16 23:28, Thomas Gleixner wrote:
> >> Patch 1-17 are trivial code improvements, bugfixes and preparation.
> >
> > Can you please move the bugfixes before the other changes, so we can
> > pick them up independently from the outcome?
> Sure,
Hi Thomas,
Thanks for review and please refer to inline comments below.
On 2014/5/16 23:28, Thomas Gleixner wrote:
> Jiang,
>
> On Fri, 16 May 2014, Jiang Liu wrote:
>
>> On x86 platforms, IRQ number are statically allocated to IOAPIC pins at boot.
>> There are two issues with this desig
On 2014/5/16 23:01, Yinghai Lu wrote:
> On Fri, May 16, 2014 at 1:05 AM, Jiang Liu wrote:
>> On x86 platforms, IRQ number are statically allocated to IOAPIC pins at boot.
>> There are two issues with this design. First it causes trouble to IOAPIC
>> hotplug because we need to allocate a block of
Jiang,
On Fri, 16 May 2014, Jiang Liu wrote:
> On x86 platforms, IRQ number are statically allocated to IOAPIC pins at boot.
> There are two issues with this design. First it causes trouble to IOAPIC
> hotplug because we need to allocate a block of IRQ numbers for each IOAPIC.
> Second it may was
On Fri, May 16, 2014 at 1:05 AM, Jiang Liu wrote:
> On x86 platforms, IRQ number are statically allocated to IOAPIC pins at boot.
> There are two issues with this design. First it causes trouble to IOAPIC
> hotplug because we need to allocate a block of IRQ numbers for each IOAPIC.
> Second it may
On x86 platforms, IRQ number are statically allocated to IOAPIC pins at boot.
There are two issues with this design. First it causes trouble to IOAPIC
hotplug because we need to allocate a block of IRQ numbers for each IOAPIC.
Second it may waste IRQ nubmers even if some IOAPIC pins are not used be
7 matches
Mail list logo
