[RFC V2 04/11] arm64: dts: mt8183: add performance state support of scpsys

[Henry Chen]

Add support for performance state of scpsys on mt8183 platform.

Signed-off-by: Henry Chen <henryc.c...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 75c4881..665d561 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/power/mt8183-power.h>
+#include <dt-bindings/soc/mtk,dvfsrc.h>
 
 / {
        compatible = "mediatek,mt8183";
@@ -251,6 +252,26 @@
                                      "vpu-3", "vpu-4", "vpu-5";
                        infracfg = <&infracfg>;
                        smi_comm = <&smi_common>;
+                       operating-points-v2 = <&dvfsrc_opp_table>;
+                       dvfsrc_opp_table: opp-table {
+                               compatible = "operating-points-v2-level";
+
+                               dvfsrc_vol_min: opp1 {
+                                       opp,level = <MT8183_DVFSRC_LEVEL_1>;
+                               };
+
+                               dvfsrc_freq_medium: opp2 {
+                                       opp,level = <MT8183_DVFSRC_LEVEL_2>;
+                               };
+
+                               dvfsrc_freq_max: opp3 {
+                                       opp,level = <MT8183_DVFSRC_LEVEL_3>;
+                               };
+
+                               dvfsrc_vol_max: opp4 {
+                                       opp,level = <MT8183_DVFSRC_LEVEL_4>;
+                               };
+                       };
                };
 
                apmixedsys: syscon@1000c000 {
-- 
1.9.1