On Wed, Dec 12, 2018 at 11:42:41AM +0100, Thierry Reding wrote:
> Did any discussion regarding the above-mentioned issues ever ensue? How
> do you want to proceed? At the very least we'll need some sort of device
> tree binding for this driver, so perhaps start with a DT binding
> proposal and take
On Thu, Mar 22, 2018 at 02:53:16PM +0100, Alvaro Gamez Machado wrote:
> This patch adds support for the IP core provided by Xilinx.
> This IP core can function as a two independent timers, but also use both
> counters as values for period and duty cycle of a PWM output.
>
> There can be many insta
This patch adds support for the IP core provided by Xilinx.
This IP core can function as a two independent timers, but also use both
counters as values for period and duty cycle of a PWM output.
There can be many instances of this IP in a design, but the first one of
them will be used to generate
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