On Fri, 6 Sep 2019 22:46:49 +0200
"H. Nikolaus Schaller" wrote:
> Hi,
>
> > Am 06.09.2019 um 05:01 schrieb Viresh Kumar :
> >
> > On 05-09-19, 07:32, Tony Lindgren wrote:
> >> * H. Nikolaus Schaller [190904 08:54]:
> >>> This adds code and tables to read the silicon revision and
> >>>
> Am 06.09.2019 um 22:46 schrieb H. Nikolaus Schaller :
>
> Hi,
>
>> Am 06.09.2019 um 05:01 schrieb Viresh Kumar :
>>
>> On 05-09-19, 07:32, Tony Lindgren wrote:
>>> * H. Nikolaus Schaller [190904 08:54]:
This adds code and tables to read the silicon revision and
eFuse (speed
Hi,
> Am 06.09.2019 um 05:01 schrieb Viresh Kumar :
>
> On 05-09-19, 07:32, Tony Lindgren wrote:
>> * H. Nikolaus Schaller [190904 08:54]:
>>> This adds code and tables to read the silicon revision and
>>> eFuse (speed binned / 720 MHz grade) bits for selecting
>>> opp-v2 table entries.
>>>
* Viresh Kumar [190906 03:05]:
> On 05-09-19, 07:32, Tony Lindgren wrote:
> > Acked-by: Tony Lindgren
>
> Do you want to pick the series instead as this has lots of DT changes
> ?
It unlikely these dts changes will conflict with anything so I
have no problem acking them for you for the next
On 05-09-19, 07:32, Tony Lindgren wrote:
> Acked-by: Tony Lindgren
Do you want to pick the series instead as this has lots of DT changes
?
--
viresh
On 05-09-19, 07:32, Tony Lindgren wrote:
> * H. Nikolaus Schaller [190904 08:54]:
> > This adds code and tables to read the silicon revision and
> > eFuse (speed binned / 720 MHz grade) bits for selecting
> > opp-v2 table entries.
> >
> > Since these bits are not always part of the syscon
* H. Nikolaus Schaller [190904 08:54]:
> This adds code and tables to read the silicon revision and
> eFuse (speed binned / 720 MHz grade) bits for selecting
> opp-v2 table entries.
>
> Since these bits are not always part of the syscon register
> range (like for am33xx, am43, dra7), we add code
This adds code and tables to read the silicon revision and
eFuse (speed binned / 720 MHz grade) bits for selecting
opp-v2 table entries.
Since these bits are not always part of the syscon register
range (like for am33xx, am43, dra7), we add code to directly
read the register values using
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