Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30/01/17 17:26, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >>> have at hand (version

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30/01/17 17:26, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >>> have at hand (version h) seems to indicate that we should, but we

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Peter, On Mon, Jan 30, 2017 at 12:26 PM, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Peter, On Mon, Jan 30, 2017 at 12:26 PM, Peter Maydell wrote: > On 30 January 2017 at 17:08, Jintack Lim wrote: >> On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >>> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >>> have at hand (version h) seems to indicate

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30 January 2017 at 17:08, Jintack Lim wrote: > On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >> have at hand (version h) seems to indicate that we should, but we

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On 30 January 2017 at 17:08, Jintack Lim wrote: > On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: >> Shouldn't we take the ENABLE bit into account? The ARMv8 ARM version I >> have at hand (version h) seems to indicate that we should, but we should >> check with the latest and greatest... >

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Marc, On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim > wrote: >> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. >> Now VMs are able to use the EL1 physical timer.

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Hi Marc, On Sun, Jan 29, 2017 at 10:44 AM, Marc Zyngier wrote: > On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim > wrote: >> Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. >> Now VMs are able to use the EL1 physical timer. >> >> Signed-off-by: Jintack Lim >> --- >>

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim wrote: > Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. > Now VMs are able to use the EL1 physical timer. > > Signed-off-by: Jintack Lim > --- > arch/arm64/kvm/sys_regs.c

Re: [RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

On Fri, Jan 27 2017 at 01:05:00 AM, Jintack Lim wrote: > Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. > Now VMs are able to use the EL1 physical timer. > > Signed-off-by: Jintack Lim > --- > arch/arm64/kvm/sys_regs.c| 32 +--- >

[RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. Now VMs are able to use the EL1 physical timer. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c| 32 +--- include/kvm/arm_arch_timer.h | 2 ++

[RFC v2 10/10] KVM: arm/arm64: Emulate the EL1 phys timer register access

Emulate read and write operations to CNTP_TVAL, CNTP_CVAL and CNTP_CTL. Now VMs are able to use the EL1 physical timer. Signed-off-by: Jintack Lim --- arch/arm64/kvm/sys_regs.c| 32 +--- include/kvm/arm_arch_timer.h | 2 ++ virt/kvm/arm/arch_timer.c| 2 +-