On Wed, Jan 21, 2015 at 05:25:32PM +0800, Zidan Wang wrote:
> On Tue, Jan 20, 2015 at 10:07:03PM -0800, Nicolin Chen wrote:
> > On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote:
> > > + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
> > > + regmap_update_bi
On Tue, Jan 20, 2015 at 10:07:03PM -0800, Nicolin Chen wrote:
> On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote:
> > +static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
>
> > + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
> > + r
On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote:
> +static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
> + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
> + regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
> +
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_fr
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