Re: [alsa-devel][PATCH v2] ASoC: wm8960: update pll and clock setting function

On Fri, Jul 03, 2015 at 05:13:42PM +0800, Zidan Wang wrote: > Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is > available for clock configure, using MCLK to provide sysclk directly, > otherwise, search a available pll out frequcncy and set pll. > > TX and RX share the same sysclk

[alsa-devel][PATCH v2] ASoC: wm8960: update pll and clock setting function

Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is available for clock configure, using MCLK to provide sysclk directly, otherwise, search a available pll out frequcncy and set pll. TX and RX share the same sysclk and bclk divider register, and have different DAC/ADC divier register.