On Thu, Mar 2, 2017 at 10:21 PM, Maxime Ripard
wrote:
> Hi Priit,
>
> On Wed, Mar 01, 2017 at 11:38:14PM +0200, Priit Laes wrote:
>> > > +/* PLL2 - Audio clock */
>> > > +static struct ccu_nm pll_audio_base_clk = {
>> > > > > > > + .enable = BIT(31),
>> > > > > > > + .n = _SUN
Hi Priit,
On Wed, Mar 01, 2017 at 11:38:14PM +0200, Priit Laes wrote:
> > > +/* PLL2 - Audio clock */
> > > +static struct ccu_nm pll_audio_base_clk = {
> > > > > > > + .enable = BIT(31),
> > > > > > > + .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
> > > > > > > + .m = _
On Tue, 2017-02-28 at 09:21 +0100, Maxime Ripard wrote:
> Hi,
>
> On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote:
> > Introduce a clock controller driver for sun7i A20 SoC.
> >
> > > > Signed-off-by: Priit Laes
> > ---
> > drivers/clk/sunxi-ng/Kconfig | 11 +
> > drivers/c
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