On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-
On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
> Hi Priit,
>
> On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > > +/* Not documented on A10 */
> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > > "pll-periph",
> > > > +
Hi Priit,
On Tue, Apr 04, 2017 at 08:09:19PM +, Priit Laes wrote:
> > > +/* Not documented on A10 */
> > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata",
> > > "pll-periph",
> > > + 0x028, BIT(14), 0);
> >
> > The rate doesn't come from pll-periph directly, does
On Mon, Mar 27, 2017 at 09:54:38AM +0200, Maxime Ripard wrote:
> Hi,
>
> Thanks a lot for working on this.
>
> On Sun, Mar 26, 2017 at 08:20:16PM +0300, Priit Laes wrote:
> > Introduce a clock controller driver for sun4i A10 and sun7i A20
> > series SoCs.
> >
> > Signed-off-by: Priit Laes
> > -
4 matches
Mail list logo
