On 1/21/2016 6:32 AM, Borislav Petkov wrote:
On Wed, Jan 20, 2016 at 12:54:51PM +0300, Dan Carpenter wrote:
+ u64 dct_sel_base_off= (u64)(pvt->dct_sel_hi & 0xFC00) << 16;
@Aravind: do you have a box with
setpci -s 18.2 0x114.l
bits [31:16] not 0?
Nope. I don't see it set
On Wed, Jan 20, 2016 at 12:54:51PM +0300, Dan Carpenter wrote:
> dct_sel_base_off is declared as a u64 but we're only using the lower 32
> bits because of a shift wrapping bug.
>
> Fixes: c8e518d5673d ('amd64_edac: Sanitize f10_get_base_addr_offset')
> Signed-off-by: Dan Carpenter
> ---
> Static
2 matches
Mail list logo