On Wed, 2019-07-03 at 19:49 +0200, Greg KH wrote:
> > +
> > + if (tx_sts & UART_SDMA0_INT) {
> > + ast_uart_sdma_write(sdma, UART_SDMA0_INT, UART_TX_SDMA_ISR);
> > + ast_sdma_bufffdone(&(sdma->dma_ch->tx_dma_info[0]));
> > + } else if (tx_sts & UART_SDMA1_INT) {
> >
On Wed, 2019-07-03 at 19:49 +0200, Greg KH wrote:
> On Tue, Jun 25, 2019 at 04:14:32PM +0530, sudheer.v wrote:
> > +#define UART_TX_R_POINT(x) (0x40 + (x * 0x20))
> > +#define UART_TX_W_POINT(x) (0x44 + (x * 0x20))
> > +#define UART_TX_SDMA_ADDR(x) (0x48 + (x * 0x20))
> > +#define UART_RX_R_POINT(x
On Tue, Jun 25, 2019 at 04:14:32PM +0530, sudheer.v wrote:
> From: sudheer veliseti
>
> UART driver for Aspeed's bmc chip AST2500
>
> Design approch:
> AST2500 has dedicated Uart DMA controller which has 12 sets of Tx and RX
> channels
> connected to UART controller directly.
> Since the DMA co
From: sudheer veliseti
UART driver for Aspeed's bmc chip AST2500
Design approch:
AST2500 has dedicated Uart DMA controller which has 12 sets of Tx and RX
channels
connected to UART controller directly.
Since the DMA controller have dedicated buffers and registers,
there would be little benifit
4 matches
Mail list logo
