On Thu, Nov 16, 2017 at 11:40:18AM +0800, Jiancheng Xue wrote:
> >> +struct clk_hisi_phase {
> >> + struct clk_hw hw;
> >> + void __iomem*reg;
> >> + u32 *phase_values;
> >> + u32 *phase_regs;
> >> + u8 phase_num;
> >
> > I do not think this
On Thu, Nov 16, 2017 at 11:40:18AM +0800, Jiancheng Xue wrote:
> >> +struct clk_hisi_phase {
> >> + struct clk_hw hw;
> >> + void __iomem*reg;
> >> + u32 *phase_values;
> >> + u32 *phase_regs;
> >> + u8 phase_num;
> >
> > I do not think this
Hi Shawn,
On 2017/11/16 10:31, Shawn Guo wrote:
> On Wed, Oct 18, 2017 at 07:00:27AM -0400, Jiancheng Xue wrote:
>> From: tianshuliang
>>
>> Add a phase clock type for HiSilicon SoCs,which supports
>> clk_set_phase operation.
>
> As the pair of phase operation, I
Hi Shawn,
On 2017/11/16 10:31, Shawn Guo wrote:
> On Wed, Oct 18, 2017 at 07:00:27AM -0400, Jiancheng Xue wrote:
>> From: tianshuliang
>>
>> Add a phase clock type for HiSilicon SoCs,which supports
>> clk_set_phase operation.
>
> As the pair of phase operation, I don't see why clk_get_phase
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