Re: [spi-devel-general] atmel_spi clock polarity

2008-02-19 Thread Atsushi Nemoto
On Mon, 18 Feb 2008 23:49:18 +0100, Haavard Skinnemoen <[EMAIL PROTECTED]> wrote: > > > CLK __|~|___|~~~|___|~~~|___|~~~|___ > > > > ... and at T1 CPOL is changed?? That's wrong. There should > > never be a partial clock period while a chipselect is active. > > While it'

Re: [spi-devel-general] atmel_spi clock polarity

2008-02-18 Thread Haavard Skinnemoen
On Mon, 18 Feb 2008 11:57:56 -0800 David Brownell <[EMAIL PROTECTED]> wrote: > On Monday 18 February 2008, Atsushi Nemoto wrote: > > IIRC the clock state follows > > CSRn.CPOL just before the real transfer. > > No ... clock state should be valid *before* chipselect goes > active. So I'm thi

Re: [spi-devel-general] atmel_spi clock polarity

2008-02-18 Thread David Brownell
On Monday 18 February 2008, Atsushi Nemoto wrote: >IIRC the clock state follows > CSRn.CPOL just before the real transfer. No ... clock state should be valid *before* chipselect goes active. So I'm thinking the patch from Haavard is likely the right change. > Like this (previous transfe