The following commit has been merged into the x86/mm branch of tip: Commit-ID: 18ec1eaf58fbf2d9009a752a102a3d8e0d905a0f Gitweb: https://git.kernel.org/tip/18ec1eaf58fbf2d9009a752a102a3d8e0d905a0f Author: Kirill A. Shutemov <kirill.shute...@linux.intel.com> AuthorDate: Fri, 13 Sep 2019 12:54:52 +03:00 Committer: Ingo Molnar <mi...@kernel.org> CommitterDate: Mon, 16 Sep 2019 16:51:20 +02:00
x86/mm: Enable 5-level paging support by default Support of boot-time switching between 4- and 5-level paging mode is upstream since 4.17. We run internal testing with 5-level paging support enabled for a while and it doesn't not cause any functional or performance regression on 4-level paging hardware. The only 5-level paging related regressions I saw were in early boot code that runs independently from CONFIG_X86_5LEVEL. The next major release of distributions expected to have CONFIG_X86_5LEVEL=y. Enable the option by default. It may help to catch obscure bugs early. Signed-off-by: Kirill A. Shutemov <kirill.shute...@linux.intel.com> Acked-by: Dave Hansen <dave.han...@linux.intel.com> Cc: Andy Lutomirski <l...@kernel.org> Cc: Borislav Petkov <b...@alien8.de> Cc: H. Peter Anvin <h...@zytor.com> Cc: Linus Torvalds <torva...@linux-foundation.org> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Rik van Riel <r...@surriel.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: linux...@kvack.org Link: https://lkml.kernel.org/r/20190913095452.40592-1-kirill.shute...@linux.intel.com Signed-off-by: Ingo Molnar <mi...@kernel.org> --- arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 58eae28..d4bbebe 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1483,6 +1483,7 @@ config X86_PAE config X86_5LEVEL bool "Enable 5-level page tables support" + default y select DYNAMIC_MEMORY_LAYOUT select SPARSEMEM_VMEMMAP depends on X86_64
