Commit-ID: 7025fdbea3a67c5980b94574b755a5fd65ea8a36 Gitweb: https://git.kernel.org/tip/7025fdbea3a67c5980b94574b755a5fd65ea8a36 Author: Florian Fainelli <f.faine...@gmail.com> AuthorDate: Mon, 13 May 2019 13:25:22 -0700 Committer: Arnaldo Carvalho de Melo <a...@redhat.com> CommitDate: Wed, 15 May 2019 16:36:49 -0300
perf vendor events arm64: Add Cortex-A57 and Cortex-A72 events The Cortex-A57 and Cortex-A72 both support all ARMv8 recommended events up to the RC_ST_SPEC (0x91) event with the exception of: - L1D_CACHE_REFILL_INNER (0x44) - L1D_CACHE_REFILL_OUTER (0x45) - L1D_TLB_RD (0x4E) - L1D_TLB_WR (0x4F) - L2D_TLB_REFILL_RD (0x5C) - L2D_TLB_REFILL_WR (0x5D) - L2D_TLB_RD (0x5E) - L2D_TLB_WR (0x5F) - STREX_SPEC (0x6F) Create an appropriate JSON file for mapping those events and update the mapfile.csv for matching the Cortex-A57 and Cortex-A72 MIDR to that file. Signed-off-by: Florian Fainelli <f.faine...@gmail.com> Reviewed-by: John Garry <john.ga...@huawei.com> Cc: Alexander Shishkin <alexander.shish...@linux.intel.com> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Ganapatrao Kulkarni <ganapatrao.kulka...@cavium.com> Cc: Jiri Olsa <jo...@redhat.com> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: Namhyung Kim <namhy...@kernel.org> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Sean V Kelley <seanvk....@oregontracks.org> Cc: Will Deacon <will.dea...@arm.com> Cc: linux-arm-ker...@lists.infradead.org (moderated list:arm pmu profiling and debugging) Link: http://lkml.kernel.org/r/20190513202522.9050-4-f.faine...@gmail.com Signed-off-by: Arnaldo Carvalho de Melo <a...@redhat.com> --- .../cortex-a57-a72}/core-imp-def.json | 92 +++++++++++++++++++--- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + 2 files changed, 81 insertions(+), 13 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json similarity index 52% copy from tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json copy to tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json index 752e47eb6977..0ac9b7927450 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a57-a72/core-imp-def.json @@ -11,12 +11,6 @@ { "ArchStdEvent": "L1D_CACHE_REFILL_WR", }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_INNER", - }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", - }, { "ArchStdEvent": "L1D_CACHE_WB_VICTIM", }, @@ -33,22 +27,25 @@ "ArchStdEvent": "L1D_TLB_REFILL_WR", }, { - "ArchStdEvent": "L1D_TLB_RD", + "ArchStdEvent": "L2D_CACHE_RD", }, { - "ArchStdEvent": "L1D_TLB_WR", + "ArchStdEvent": "L2D_CACHE_WR", }, { - "ArchStdEvent": "L2D_TLB_REFILL_RD", + "ArchStdEvent": "L2D_CACHE_REFILL_RD", }, { - "ArchStdEvent": "L2D_TLB_REFILL_WR", + "ArchStdEvent": "L2D_CACHE_REFILL_WR", }, { - "ArchStdEvent": "L2D_TLB_RD", + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", }, { - "ArchStdEvent": "L2D_TLB_WR", + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", }, { "ArchStdEvent": "BUS_ACCESS_RD", @@ -56,6 +53,18 @@ { "ArchStdEvent": "BUS_ACCESS_WR", }, + { + "ArchStdEvent": "BUS_ACCESS_SHARED", + }, + { + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED", + }, + { + "ArchStdEvent": "BUS_ACCESS_NORMAL", + }, + { + "ArchStdEvent": "BUS_ACCESS_PERIPH", + }, { "ArchStdEvent": "MEM_ACCESS_RD", }, @@ -71,6 +80,57 @@ { "ArchStdEvent": "UNALIGNED_LDST_SPEC", }, + { + "ArchStdEvent": "LDREX_SPEC", + }, + { + "ArchStdEvent": "STREX_PASS_SPEC", + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC", + }, + { + "ArchStdEvent": "LD_SPEC", + }, + { + "ArchStdEvent": "ST_SPEC", + }, + { + "ArchStdEvent": "LDST_SPEC", + }, + { + "ArchStdEvent": "DP_SPEC", + }, + { + "ArchStdEvent": "ASE_SPEC", + }, + { + "ArchStdEvent": "VFP_SPEC", + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + }, + { + "ArchStdEvent": "BR_IMMED_SPEC", + }, + { + "ArchStdEvent": "BR_RETURN_SPEC", + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + }, + { + "ArchStdEvent": "ISB_SPEC", + }, + { + "ArchStdEvent": "DSB_SPEC", + }, + { + "ArchStdEvent": "DMB_SPEC", + }, { "ArchStdEvent": "EXC_UNDEF", }, @@ -109,5 +169,11 @@ }, { "ArchStdEvent": "EXC_TRAP_FIQ", - } + }, + { + "ArchStdEvent": "RC_LD_SPEC", + }, + { + "ArchStdEvent": "RC_ST_SPEC", + }, ] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 013155f1eb58..927fcddcb4aa 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -14,6 +14,8 @@ #Family-model,Version,Filename,EventType 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core +0x00000000410fd070,v1,arm/cortex-a57-a72,core +0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000480fd010,v1,hisilicon/hip08,core
