On Thu, 2021-01-28 at 16:27 +0200, Mika Westerberg wrote:
> Hi,
>
> On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote:
> > From: Mingchuang Qiao
> >
> > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
> > configured in pci_configure_ltr(). If de
Hi,
On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote:
> From: Mingchuang Qiao
>
> In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
> configured in pci_configure_ltr(). If device and bridge both support LTR
> mechanism, the "LTR Mechanism Enable"
From: Mingchuang Qiao
In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is
configured in pci_configure_ltr(). If device and bridge both support LTR
mechanism, the "LTR Mechanism Enable" bit of device and bridge will be
enabled in DEVCTL2 register. And pci_dev->ltr_path will be
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