Re: [v2] PCI: Avoid unsync of LTR mechanism configuration

2021-01-31 Thread Mingchuang Qiao
On Thu, 2021-01-28 at 16:27 +0200, Mika Westerberg wrote: > Hi, > > On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote: > > From: Mingchuang Qiao > > > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > > configured in pci_configure_ltr(). If de

Re: [v2] PCI: Avoid unsync of LTR mechanism configuration

2021-01-28 Thread Mika Westerberg
Hi, On Thu, Jan 28, 2021 at 06:05:31PM +0800, mingchuang.q...@mediatek.com wrote: > From: Mingchuang Qiao > > In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is > configured in pci_configure_ltr(). If device and bridge both support LTR > mechanism, the "LTR Mechanism Enable"

[v2] PCI: Avoid unsync of LTR mechanism configuration

2021-01-28 Thread mingchuang.qiao
From: Mingchuang Qiao In bus scan flow, the "LTR Mechanism Enable" bit of DEVCTL2 register is configured in pci_configure_ltr(). If device and bridge both support LTR mechanism, the "LTR Mechanism Enable" bit of device and bridge will be enabled in DEVCTL2 register. And pci_dev->ltr_path will be