> > > >>> Where did you get this information that the register on LS1043
> > > >>> and
> > > >>> LS1046 is bit reversed? I cannot find such information in the RM.
> > > >>> And does this mean all other SCFG registers are also bit reversed?
> > > >>> If this is some information that is not
; Z.q.
> > Hou ; t...@linutronix.de; ja...@lakedaemon.net;
> > m...@kernel.org
> > Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> > ; Xiaobo Xie ; linux-arm-
> > ker...@lists.infradead.org
> > Subject: Re: [EXT] Re: [v2 01/11] irqchip: l
nel.org
> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> ; Xiaobo Xie ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A
> external interrupt
>
> On 02/11/2020 22.22, Leo Li wrote:
>
On 02/11/2020 22.22, Leo Li wrote:
>>>
>>> Where did you get this information that the register on LS1043 and
>>> LS1046 is bit reversed? I cannot find such information in the RM.
>>> And does this mean all other SCFG registers are also bit reversed? If
>>> this is some information that is not
gt; m...@kernel.org
> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> ; Xiaobo Xie ; linux-arm-
> ker...@lists.infradead.org
> Subject: RE: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A
> external interrupt
>
> > > >
> >
> > >
> > > Caution: EXT Email
> > >
> > > On 27/10/2020 05.46, Biwen Li wrote:
> > > > From: Hou Zhiqiang
> > > >
> > > > Add an new IRQ chip declaration for LS1043A and LS1088A
> > > > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> SCFG_INTPCR[31:0]
> > > > of these SoCs is
kernel.org
> Cc: devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; Jiafei Pan
> ; Xiaobo Xie ; linux-arm-
> ker...@lists.infradead.org
> Subject: RE: [EXT] Re: [v2 01/11] irqchip: ls-extirq: Add LS1043A, LS1088A
> external interrupt
>
> >
> > Caution: EXT Email
&
> >> On 2020-10-27 04:46, Biwen Li wrote:
> >> > From: Hou Zhiqiang
> >> >
> >> > Add an new IRQ chip declaration for LS1043A and LS1088A
> >> > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> >> > SCFG_INTPCR[31:0]
> >> > of these SoCs is stored/read as SCFG_INTPCR[0:31]
On 2020-10-27 10:35, Biwen Li (OSS) wrote:
On 2020-10-27 04:46, Biwen Li wrote:
> From: Hou Zhiqiang
>
> Add an new IRQ chip declaration for LS1043A and LS1088A
> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> SCFG_INTPCR[31:0]
> of these SoCs is stored/read as SCFG_INTPCR[0:31]
>
> On 2020-10-27 04:46, Biwen Li wrote:
> > From: Hou Zhiqiang
> >
> > Add an new IRQ chip declaration for LS1043A and LS1088A
> > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
> > SCFG_INTPCR[31:0]
> > of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit
> > reverse)
On 2020-10-27 04:46, Biwen Li wrote:
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A.
SCFG_INTPCR[31:0]
of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit
reverse)
- compatible
>
> Caution: EXT Email
>
> On 27/10/2020 05.46, Biwen Li wrote:
> > From: Hou Zhiqiang
> >
> > Add an new IRQ chip declaration for LS1043A and LS1088A
> > - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. SCFG_INTPCR[31:0]
> > of these SoCs is stored/read as SCFG_INTPCR[0:31]
On 27/10/2020 05.46, Biwen Li wrote:
> From: Hou Zhiqiang
>
> Add an new IRQ chip declaration for LS1043A and LS1088A
> - compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. SCFG_INTPCR[31:0]
> of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit
> reverse)
s/defaultly/by
From: Hou Zhiqiang
Add an new IRQ chip declaration for LS1043A and LS1088A
- compatible "fsl,ls1043a-extirq" for LS1043A, LS1046A. SCFG_INTPCR[31:0]
of these SoCs is stored/read as SCFG_INTPCR[0:31] defaultly(bit
reverse)
- compatible "fsl,ls1088a-extirq" for LS1088A, LS208xA, LX216xA
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