I just submitted a version of the driver without copy-pasted chip-select
code. The PATCH v4 version uses a pair of zero-byte SPI transfers to
control the CS line.
I didn't get a response from the linux-spi mailing list, but in my
opinion they're probably not going to want spi_set_cs to become
Hi Joel,
On Mon, Oct 24, 2016 at 9:51 PM, Joel Holdsworth
wrote:
> I think my set_cs() function is ok-ish. It's copied from spi_set_cs() in
> drivers/spi/spi.c . This function is a static internal helper, so I
> copy/pasted the function into the ice40 driver. Given that it's only 4-lines
> of co
On Mon, Oct 24, 2016 at 11:05:28PM -0600, Joel Holdsworth wrote:
> Only being able to load firmware from kernel C-code is rather a limitation -
> though I suppose the framework is quite early in development.
I agree this is a limitation. To expand a bit on what Alan said. For the
last year(?) or
Hi Alan
> Yes! I have submitted patches for doing exactly that. About to
> submit v21. Here's patch 1 of v20:
>
> https://patchwork.kernel.org/patch/9379859/
That's really cool. I hope it gets accepted.
>> and/or if there were any patches for loading
>> firmware from userspace - somethin
On Tue, 25 Oct 2016, Joel Holdsworth wrote:
>
> > Hi Joel,
> >
> > Thanks for submitting your driver!
> >
> > I didn't see any huge problems, just minor things below...
> >
> > Alan
> >
>
> Hi Alan, Thanks for your feedback. I've implemented all your suggestions and
> I'll resubmit.
>
> I h
Hi Joel,
Thanks for submitting your driver!
I didn't see any huge problems, just minor things below...
Alan
Hi Alan, Thanks for your feedback. I've implemented all your suggestions
and I'll resubmit.
I had a question about the status of the fpga-manager framework. Is
there active work
On 10/24/2016 04:28 PM, Moritz Fischer wrote:
Hi Joel,
Ha, finally someone beat me to submitting my driver,
I had an ugly hack to bitbang the SPI since I couldn't figure
out a good way to assert the creset after the CS.
Thanks!
Hi Moritz - yeah I figured someone might have a driver in the
Hi Joel,
Ha, finally someone beat me to submitting my driver,
I had an ugly hack to bitbang the SPI since I couldn't figure
out a good way to assert the creset after the CS.
Thanks!
On Mon, Oct 24, 2016 at 04:55:43PM -0500, atull wrote:
> On Mon, 24 Oct 2016, Joel Holdsworth wrote:
>
> > The La
On Mon, 24 Oct 2016, Joel Holdsworth wrote:
> The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
> and very regular structure, designed for low-cost, high-volume consumer
> and system applications.
>
> This patch adds support to the FPGA manager for configuring the SRAM of
>
The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
and very regular structure, designed for low-cost, high-volume consumer
and system applications.
This patch adds support to the FPGA manager for configuring the SRAM of
iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite a
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