Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2017-01-03 Thread Ricardo Neri
On Fri, 2016-12-30 at 18:07 -0800, Andy Lutomirski wrote: > On Thu, Dec 29, 2016 at 9:23 PM, Ricardo Neri > wrote: > > On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > >> > >> >> > + if (nr_copied > 0) > >> >> > +

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2017-01-03 Thread Ricardo Neri
On Fri, 2016-12-30 at 18:07 -0800, Andy Lutomirski wrote: > On Thu, Dec 29, 2016 at 9:23 PM, Ricardo Neri > wrote: > > On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > >> > >> >> > + if (nr_copied > 0) > >> >> > + return -EFAULT; > >> >> > >> >>

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-30 Thread Andy Lutomirski
On Thu, Dec 29, 2016 at 9:23 PM, Ricardo Neri wrote: > On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: >> >> >> > + if (nr_copied > 0) >> >> > + return -EFAULT; >> >> >> >> This should be the only EFAULT case.

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-30 Thread Andy Lutomirski
On Thu, Dec 29, 2016 at 9:23 PM, Ricardo Neri wrote: > On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: >> >> >> > + if (nr_copied > 0) >> >> > + return -EFAULT; >> >> >> >> This should be the only EFAULT case. >> > Should this be EFAULT event if the

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-29 Thread Ricardo Neri
On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > On Tue, Dec 27, 2016 at 4:39 PM, Ricardo Neri > wrote: > > On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > >> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > >>

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-29 Thread Ricardo Neri
On Tue, 2016-12-27 at 16:48 -0800, Andy Lutomirski wrote: > On Tue, Dec 27, 2016 at 4:39 PM, Ricardo Neri > wrote: > > On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > >> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > >> wrote: > >> > The feature User-Mode Instruction Prevention

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Andy Lutomirski
On Tue, Dec 27, 2016 at 4:39 PM, Ricardo Neri wrote: > On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: >> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri >> wrote: >> > The feature User-Mode Instruction

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Andy Lutomirski
On Tue, Dec 27, 2016 at 4:39 PM, Ricardo Neri wrote: > On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: >> On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri >> wrote: >> > The feature User-Mode Instruction Prevention present in recent Intel >> > processor prevents a group of instructions

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Ricardo Neri
On Mon, 2016-12-26 at 00:49 +0900, Masami Hiramatsu wrote: > On Fri, 23 Dec 2016 17:37:43 -0800 > Ricardo Neri wrote: > > > +static int __identify_insn(struct insn *insn) > > +{ > > + /* by getting modrm we also get the opcode */ > > +

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Ricardo Neri
On Mon, 2016-12-26 at 00:49 +0900, Masami Hiramatsu wrote: > On Fri, 23 Dec 2016 17:37:43 -0800 > Ricardo Neri wrote: > > > +static int __identify_insn(struct insn *insn) > > +{ > > + /* by getting modrm we also get the opcode */ > > + insn_get_modrm(insn); > > + if (insn->opcode.bytes[0]

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Ricardo Neri
On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > wrote: > > The feature User-Mode Instruction Prevention present in recent Intel > > processor prevents a group of instructions from being executed

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-27 Thread Ricardo Neri
On Fri, 2016-12-23 at 18:11 -0800, Andy Lutomirski wrote: > On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri > wrote: > > The feature User-Mode Instruction Prevention present in recent Intel > > processor prevents a group of instructions from being executed with > > CPL > 0. Otherwise, a general

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-25 Thread Masami Hiramatsu
On Fri, 23 Dec 2016 17:37:43 -0800 Ricardo Neri wrote: > +static int __identify_insn(struct insn *insn) > +{ > + /* by getting modrm we also get the opcode */ > + insn_get_modrm(insn); > + if (insn->opcode.bytes[0] != 0xf) > + return

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-25 Thread Masami Hiramatsu
On Fri, 23 Dec 2016 17:37:43 -0800 Ricardo Neri wrote: > +static int __identify_insn(struct insn *insn) > +{ > + /* by getting modrm we also get the opcode */ > + insn_get_modrm(insn); > + if (insn->opcode.bytes[0] != 0xf) > + return -EINVAL; > + > + if

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-23 Thread Andy Lutomirski
On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri wrote: > The feature User-Mode Instruction Prevention present in recent Intel > processor prevents a group of instructions from being executed with > CPL > 0. Otherwise, a general protection fault is issued. > >

Re: [v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-23 Thread Andy Lutomirski
On Fri, Dec 23, 2016 at 5:37 PM, Ricardo Neri wrote: > The feature User-Mode Instruction Prevention present in recent Intel > processor prevents a group of instructions from being executed with > CPL > 0. Otherwise, a general protection fault is issued. > > Rather than relaying this fault to the

[v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-23 Thread Ricardo Neri
The feature User-Mode Instruction Prevention present in recent Intel processor prevents a group of instructions from being executed with CPL > 0. Otherwise, a general protection fault is issued. Rather than relaying this fault to the user space (in the form of a SIGSEGV signal), the instructions

[v2 5/7] x86: Add emulation code for UMIP instructions

2016-12-23 Thread Ricardo Neri
The feature User-Mode Instruction Prevention present in recent Intel processor prevents a group of instructions from being executed with CPL > 0. Otherwise, a general protection fault is issued. Rather than relaying this fault to the user space (in the form of a SIGSEGV signal), the instructions