Re: [v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue

Hi Biao On 5/24/19 8:26 AM, Biao Huang wrote: The specific clk_csr value can be zero, and stmmac_clk is necessary for MDC clock which can be set dynamically. So, change the condition from plat->clk_csr to plat->stmmac_clk to fix clk_csr can't be zero issue. Fixes: cd7201f477b9 ("stmmac: MDC clo

[v4, PATCH 2/3] net: stmmac: fix csr_clk can't be zero issue

The specific clk_csr value can be zero, and stmmac_clk is necessary for MDC clock which can be set dynamically. So, change the condition from plat->clk_csr to plat->stmmac_clk to fix clk_csr can't be zero issue. Fixes: cd7201f477b9 ("stmmac: MDC clock dynamically based on the csr clock input") Si