[v4, PATCH 3/3] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail

[Biao Huang]

1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Fixes: 9992f37e346b ("stmmac: dwmac-mediatek: add support for mt2712")
Signed-off-by: Biao Huang <biao.hu...@mediatek.com>
---
 .../net/ethernet/stmicro/stmmac/dwmac-mediatek.c   |    2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index bf25629..126b66b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device 
*pdev)
                return PTR_ERR(plat_dat);
 
        plat_dat->interface = priv_plat->phy_mode;
-       /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
-       plat_dat->clk_csr = 5;
        plat_dat->has_gmac4 = 1;
        plat_dat->has_gmac = 0;
        plat_dat->pmt = 0;
-- 
1.7.9.5