On Mon, 2020-12-28 at 15:12 +, Marc Zyngier wrote:
> On Mon, 28 Dec 2020 12:01:57 +,
> Jianjun Wang wrote:
> >
> > On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
>
> Dropped , as it
> bounces:
>
> : host
> mailgw01.mediatek.com[216.200.240.184] said: 550 Relaying mail
On Mon, 28 Dec 2020 12:01:57 +,
Jianjun Wang wrote:
>
> On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
Dropped , as it
bounces:
: host
mailgw01.mediatek.com[216.200.240.184] said: 550 Relaying mail to
project_global_chrome_upstream_gr...@mediatek.com is not allowed (in reply
On Fri, 2020-12-25 at 19:22 +, Marc Zyngier wrote:
> Hi Jianjun,
>
> On Fri, 25 Dec 2020 10:03:07 +,
> Jianjun Wang wrote:
> >
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supports Gen3 speed and
> > up to 256 MSI int
Hi Jianjun,
On Fri, 25 Dec 2020 10:03:07 +,
Jianjun Wang wrote:
>
> MediaTek's PCIe host controller has three generation HWs, the new
> generation HW is an individual bridge, it supports Gen3 speed and
> up to 256 MSI interrupt numbers for multi-function devices.
>
> Add support for new Gen
MediaTek's PCIe host controller has three generation HWs, the new
generation HW is an individual bridge, it supports Gen3 speed and
up to 256 MSI interrupt numbers for multi-function devices.
Add support for new Gen3 controller which can be found on MT8192.
Signed-off-by: Jianjun Wang
Acked-by:
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