[v6 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-12 Thread Geetha sowjanya
From: Linu Cherian Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following

[v6 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-05-12 Thread Geetha sowjanya
From: Linu Cherian Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines and also MSI for gerror, eventq and cmdq-sync The following patchset does software