I was wondering, on dual processor MB's, Intel uses dedicated memory for
each cpu 6 memchips in the X5XXX series, and to access the memory
of the other chip's cores, the memory has to be transferred over the QPI
bus.
So wouldn't it be of benefit if such dual chip configurations were to
be
On Mon, 2012-09-17 at 11:00 -0700, Linda Walsh wrote:
> I was wondering, on dual processor MB's, Intel uses dedicated memory for
>
> each cpu 6 memchips in the X5XXX series, and to access the memory
> of the other chip's cores, the memory has to be transferred over the QPI
> bus.
>
> So wo
On Tue, Sep 18, 2012 at 2:00 AM, Linda Walsh wrote:
> Does the kernel support scheduling based on the different speed of
> memory between "on die" vs. "off die"? I was surprised to see
> that it viewed my system as 1 NUMA node with all 12 on 1 node -- when
> I know that it is physically organize
Jike Song wrote:
Do you have anything printed with:
# acpidump -a --table SRAT
It prints out a bunch of stuff, but the word SRAT wasn't in the
output.
I don't remember a node interleaving in the BIOS -- There's a ECC mode,
where I only get 4/6 slots for usable memory, or an optimized mode
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