> Agreed. No hurry, but thanks to Alok for reminding us.
> CC'ing Ben since he's the one most active in mmu_gathering these days.
> CC'ing Thomas lest he's puzzling over it in the x86 merge.
Hrm... yes, that stuff sucks. I've had my work on mmu gather on hold
since KS due to other priorities sho
On Mon, 15 Oct 2007, Nick Piggin wrote:
> On Monday 15 October 2007 16:54, Alok kataria wrote:
> >
> > Looking at the tlb_flush code path and its co-relation with
> > ARCH_FREE_PTE_NR, on x86-64 architecture. I think we still don't use
> > the ARCH_FREE_PTE_NR of 5350 as the caching value for the m
On Monday 15 October 2007 16:54, Alok kataria wrote:
> Hi,
>
> Looking at the tlb_flush code path and its co-relation with
> ARCH_FREE_PTE_NR, on x86-64 architecture. I think we still don't use
> the ARCH_FREE_PTE_NR of 5350 as the caching value for the mmu_gathers
> structure, instead fallback to
Hi,
Looking at the tlb_flush code path and its co-relation with
ARCH_FREE_PTE_NR, on x86-64 architecture. I think we still don't use
the ARCH_FREE_PTE_NR of 5350 as the caching value for the mmu_gathers
structure, instead fallback to using 506 due to some typo errors in
the code.
Found this link
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