On 06/03/2015 03:25 PM, Michael Turquette wrote:
Quoting Mike Looijmans (2015-06-02 22:25:19)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..1c31704 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -78,6 +78,23 @@ config COMMON_CLK_SI570
This
Quoting Mike Looijmans (2015-06-02 22:25:19)
> This driver supports the TI CDCE925 programmable clock synthesizer.
> The chip contains two PLLs with spread-spectrum clocking support and
> five output dividers. The driver only supports the following setup,
> and uses a fixed setting for the output
On 06/03/2015 03:25 PM, Michael Turquette wrote:
Quoting Mike Looijmans (2015-06-02 22:25:19)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..1c31704 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -78,6 +78,23 @@ config COMMON_CLK_SI570
This
Quoting Mike Looijmans (2015-06-02 22:25:19)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
On Tue, 2015-06-02 at 10:43 +0200, Mike Looijmans wrote:
> Out of curiousity, I did try a compile on the x86 host, but couldn't select
> the driver because it depends on CONFIG_OF, so I just compiled if for the ARM
> target to verify that it still compiles in kernel 4.1. How did you manage to
>
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(>dev, "%s(%u) %#x %#x\n", __func__,
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(>dev, "%s(%u) %#x %#x\n", __func__,
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
> --- /dev/null
> +++ b/drivers/clk/clk-cdce925.c
> +static int cdce925_regmap_i2c_write(
> + void *context, const void *data, size_t count)
> + dev_dbg(>dev, "%s(%u) %#x %#x\n", __func__, count,
> +
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(i2c-dev, %s(%u) %#x %#x\n, __func__, count,
+ reg_data[0],
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(i2c-dev, %s(%u) %#x %#x\n, __func__,
On 02-06-15 09:50, Paul Bolle wrote:
On Mon, 2015-06-01 at 12:13 +0200, Mike Looijmans wrote:
--- /dev/null
+++ b/drivers/clk/clk-cdce925.c
+static int cdce925_regmap_i2c_write(
+ void *context, const void *data, size_t count)
+ dev_dbg(i2c-dev, %s(%u) %#x %#x\n, __func__,
On Tue, 2015-06-02 at 10:43 +0200, Mike Looijmans wrote:
Out of curiousity, I did try a compile on the x86 host, but couldn't select
the driver because it depends on CONFIG_OF, so I just compiled if for the ARM
target to verify that it still compiles in kernel 4.1. How did you manage to
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
On 28-05-15 23:48, Michael Turquette wrote:
Hi Mike,
Quoting Mike Looijmans (2014-12-03 23:26:15)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the
On 28-05-15 23:48, Michael Turquette wrote:
Hi Mike,
Quoting Mike Looijmans (2014-12-03 23:26:15)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the
Hello,
I was wondering what happened to this patch? Should I resubmit?
Mike.
On 04-12-14 08:26, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
Hello,
I was wondering what happened to this patch? Should I resubmit?
Mike.
On 04-12-14 08:26, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
On 12-01-15 04:04, Mike Turquette wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Just another ping, you haven't
On 12-01-15 04:04, Mike Turquette wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans mike.looijm...@topic.nl wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Just
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans wrote:
> Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Regards,
Mike
>
> Mike.
>
> On 12/04/2014 08:26 AM, Mike Looijmans wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans mike.looijm...@topic.nl wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Regards,
Mike
Mike.
On 12/04/2014 08:26 AM, Mike
Just a ping to inform if you've had had time to look at this?
Mike.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
Just a ping to inform if you've had had time to look at this?
Mike.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only
Just a ping to ask for attention. Anyone care to review, comment or otherwise
provide some feedback?
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five
Just a ping to ask for attention. Anyone care to review, comment or otherwise
provide some feedback?
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
This patch contains a driver for an I2C controlled clock synthesizer.
We've been using this driver for a while for creating clock signals
for HDMI and audio.
The only thing missing in this patch is the devicetree binding
information, I intend to add that in a later patch.
Please
This patch contains a driver for an I2C controlled clock synthesizer.
We've been using this driver for a while for creating clock signals
for HDMI and audio.
The only thing missing in this patch is the devicetree binding
information, I intend to add that in a later patch.
Please
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and
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