On Tue, Mar 30, 2021 at 4:29 AM Kishon Vijay Abraham I wrote:
>
> Hi Rob,
>
> On 26/03/21 5:08 am, Rob Herring wrote:
> > On Thu, Mar 25, 2021 at 02:30:21PM +0530, Kishon Vijay Abraham I wrote:
> >> Add PCIe host mode dt-bindings for TI's AM65 SoC.
> >>
> &
On 15/04/2021 13:48, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple Root Ports, and each RCiEP is
registered as a PMU in /sys/bus/event_source/devices, so users can
On 19/04/2021 14:21, Yicong Yang wrote:
On 2021/4/19 19:17, Suzuki K Poulose wrote:
On 17/04/2021 11:17, Yicong Yang wrote:
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing
The kernel has xmit_more facility that hints the networking driver xmit
path about whether more packets are coming soon. This information can be
used to avoid unnecessary expensive PCIe transaction per tx packet at a
slight increase in latency.
Max TX pps on Mikrotik 10/25G NIC in a Threadripper
revert the original change, just use pcie_set_readrq() now instead of
changing the PCIe capability register directly.
Fixes: 2df49d365498 ("r8169: remove fiddling with the PCIe max read request
size")
Signed-off-by: Heiner Kallweit
Signed-off-by: David S. Miller
Signed-off-by: S
From: Heiner Kallweit
[ Upstream commit 2df49d36549808a7357ad9f78b7a8e39516e7809 ]
The attempt to improve performance by changing the PCIe max read request
size was added in the vendor driver more than 10 years back and copied
to r8169 driver. In the vendor driver this has been removed long ago
On 2021/4/19 19:17, Suzuki K Poulose wrote:
> On 17/04/2021 11:17, Yicong Yang wrote:
>> [RESEND with perf and coresight folks Cc'ed]
>>
>> HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
>> integrated Endpoint (RCiEP) device, providing the capabilit
On 2021/4/17 21:56, Alexander Shishkin wrote:
> Yicong Yang writes:
>
>> The reason for not using perf is because there is no current support
>> for uncore tracing in the perf facilities.
>
> Not unless you count
>
> $ perf list|grep -ic uncore
> 77
>
these are uncore events probably do not
On 17/04/2021 11:17, Yicong Yang wrote:
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing the capability
to dynamically monitor and tune the PCIe traffic (tune),
and trace the TLP headers
From: Alexander Antonov
Introduce helper functions to control PCIe root ports list.
These helpers will be used in the follow-up patch.
Acked-by: Namhyung Kim
Signed-off-by: Alexander Antonov
---
tools/perf/arch/x86/util/iostat.c | 110 ++
1 file changed, 110
1 +
.../pci/controller/cadence/pcie-cadence-ep.c | 285 ++
drivers/pci/controller/cadence/pcie-cadence.h | 7 +
.../pci/controller/dwc/pcie-designware-ep.c | 36 +--
drivers/pci/controller/pcie-rcar-ep.c | 19 +-
drivers/pci/controller/pcie-rockchip-ep.c | 18 +-
Add entries for Toshiba Visconti PCIe controller binding and driver.
Signed-off-by: Nobuhiro Iwamatsu
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a154939ae27..3e5187c5b8d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2621,11 +2621,13
Add support to PCIe RC controller on Toshiba Visconti ARM SoCs. PCIe controller
is based of Synopsys
DesignWare PCIe core.
This patch does not yet use the clock framework to control the clock. This will
be replaced in the
future.
Signed-off-by: Yuji Ishikawa
Signed-off-by: Nobuhiro Iwamatsu
This commit adds the Device Tree binding documentation that allows
to describe the PCIe controller found in Toshiba Visconti SoCs.
Signed-off-by: Nobuhiro Iwamatsu
---
.../bindings/pci/toshiba,visconti-pcie.yaml | 110 ++
1 file changed, 110 insertions(+)
create mode 100644
Hi,
This series is the PCIe driver for Toshiba's ARM SoC, Visconti[0].
This provides DT binding documentation, device driver, MAINTAINER files.
Best regards,
Nobuhiro
[0]:
https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html
dt
mpatible = "sifive,fu740-c000-uart",
> > > "sifive,uart0";
> > > @@ -288,5 +289,38 @@ gpio: gpio@1006 {
> > > clocks = < PRCI_CLK_PCLK>;
> > > status = "disabled";
> > > };
#reset-cells = <1>;
> > };
> > uart0: serial@1001 {
> > compatible = "sifive,fu740-c000-uart", "sifive,uart0";
> > @@ -288,5 +289,38 @@ gpio: gpio@1006 {
> >
Yicong Yang writes:
> The reason for not using perf is because there is no current support
> for uncore tracing in the perf facilities.
Not unless you count
$ perf list|grep -ic uncore
77
> We have our own format
> of data and don't need perf doing the parsing.
Perf has AUX buffers, which
HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex
integrated Endpoint(RCiEP) device, providing the capability
to dynamically monitor and tune the PCIe traffic(tune),
and trace the TLP headers(trace).
Add the driver for the device to enable the trace function. The driver
will create
[RESEND with perf and coresight folks Cc'ed]
HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
integrated Endpoint (RCiEP) device, providing the capability
to dynamically monitor and tune the PCIe traffic (tune),
and trace the TLP headers (trace).
PTT tune is designed
Add tune function for the HiSilicon Tune and Trace device. The interface
of tune is also exposed through debugfs.
Signed-off-by: Yicong Yang
---
drivers/hwtracing/hisilicon/hisi_ptt.c | 187 +
1 file changed, 187 insertions(+)
diff --git
Hi,
On Wed, Apr 7, 2021 at 2:35 PM Kornel Duleba wrote:
>
> Currently all PCIE windows point to bus address 0x0, which does not match
> the values obtained from hardware during EA.
> Replace those values with CPU addresses, since in reality we
> have a 1:1 mapping between the two.
t; report. I understand it to resolve an issue during link retraining to a
> higher speed on boot, not during a bus reset. Pali can correct if I'm
> wrong. Thanks,
These two issues are are related. Both operations (PCIe Hot Reset and
PCIe Link Retraining) cause reset of ath chips. Seems that
t; [+cc Alex]
> >>
> >> On Fri, Apr 09, 2021 at 11:26:33AM +0200, Ingmar Klein wrote:
> >>> Edit: Retry, as I did not consider, that my mail-client would make this
> >>> party html.
> >>>
> >>> Dear maintainers,
> >>> I recently
wrote:
[+cc Alex]
On Fri, Apr 09, 2021 at 11:26:33AM +0200, Ingmar Klein wrote:
Edit: Retry, as I did not consider, that my mail-client would make this
party html.
Dear maintainers,
I recently encountered an issue on my Proxmox server system, that
includes a Qualcomm QCA6174 m.2 PCIe wifi
' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Qi-Liu/drivers-perf-hisi-Add-support-for-PCIe-PMU/20210415-204823
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
7f75285ca572eaabc028cf78c6ab5473d0d160be
config: sh
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple Root Ports, and each RCiEP is
registered as a PMU in /sys/bus/event_source/devices, so users can
select target PMU, and use filter
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported on
HiSilicon HIP09 platform. Document it to provide guidance on how to
use it.
Signed-off-by: Qi Liu
---
Documentation/admin-guide/perf/hisi-pcie-pmu.rst | 104 +++
1 file changed, 104 insertions
This patchset adds support for HiSilicon PCIe Performance Monitoring
Unit(PMU). It is a PCIe Root Complex integrated End Point(RCiEP) device
added on Hip09. Each PCIe Core has a PMU RCiEP to monitor multi root
ports and all Endpoints downstream these root ports.
HiSilicon PCIe PMU is supported
@vger.kernel.org;
lvjianmin
Subject: [PATCH] ACPICA: Events: support fixed pcie wake event
From: lvjianmin
Some chipsets support fixed pcie wake event which is defined in the PM1 block,
such as LS7A1000 of Loongson company, so we add code to handle it.
Signed-off-by: lvjianmin
diff --git
; I recently encountered an issue on my Proxmox server system, that
> > includes a Qualcomm QCA6174 m.2 PCIe wifi module.
> > https://deviwiki.com/wiki/AIRETOS_AFX-QCA6174-NX
> >
> > On system boot and subsequent virtual machine start (with passed-through
> > Q
[+cc Alex]
On Fri, Apr 09, 2021 at 11:26:33AM +0200, Ingmar Klein wrote:
> Edit: Retry, as I did not consider, that my mail-client would make this
> party html.
>
> Dear maintainers,
> I recently encountered an issue on my Proxmox server system, that
> includes a Qualcomm QCA
From: Ben Peled
Add system controller and reset bit to each pcie to enable pcie mac reset
Signed-off-by: Ben Peled
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts
Hi Shawn:
Regarding Lucas' advice, this patch should be split out and post for you to
pick up into DT tree.
Since the other two patches are accepted by PCIe tree now.
Can you help to pick up this patch?
Thanks in advanced.
https://patchwork.kernel.org/project/linux-pci/patch/1616661882-26487-3
Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
the VREG_BYPASS bits of GPR registers should be cleared from default
value 1b'1 to 1b'0
On Tue, Apr 13, 2021 at 11:42:15PM +0530, Vidya Sagar wrote:
> On 4/13/2021 3:23 AM, Bjorn Helgaas wrote:
> > The existing port services (AER, DPC, hotplug, etc) are things the
> > device advertises via the PCI Capabilities defined by the generic PCIe
> > spec, and in m
On 4/13/2021 11:43 PM, Rob Herring wrote:
External email: Use caution opening links or attachments
On Mon, Apr 12, 2021 at 12:01 PM Vidya Sagar wrote:
Hi
I'm starting this mail to seek advice on the best approach to be taken
to add support for the driver of the PCIe root port's DMA
On Mon, Apr 12, 2021 at 12:01 PM Vidya Sagar wrote:
>
> Hi
> I'm starting this mail to seek advice on the best approach to be taken
> to add support for the driver of the PCIe root port's DMA engine.
> To give some background, Tegra194's PCIe IPs are dual-mode PCIe IPs i.e.
>
for the driver of the PCIe root port's DMA engine.
To give some background, Tegra194's PCIe IPs are dual-mode PCIe IPs i.e.
they work either in the root port mode or in the endpoint mode based on the
boot time configuration.
Since the PCIe hardware IP as such is the same for both (RP and EP) modes
On 13/04/2021 10:12, liuqi (BA) wrote:
I do wonder why we even need maintain pcie_pmu->cpumask
Can't we just use cpu_online_mask as appropiate instead?
?
Sorry, missed it yesterday.
It seems that cpumask is always same as cpu_online_mask, So do we need
to reserve the cpumask sysfs
Hi John,
On 2021/4/13 1:21, John Garry wrote:
On 12/04/2021 14:34, liuqi (BA) wrote:
Hi John,
Thanks for reviewing this.
On 2021/4/9 18:22, John Garry wrote:
On 09/04/2021 10:05, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth
[+cc Matthew for portdrv comment]
On Mon, Apr 12, 2021 at 10:31:02PM +0530, Vidya Sagar wrote:
> Hi
> I'm starting this mail to seek advice on the best approach to be taken to
> add support for the driver of the PCIe root port's DMA engine.
> To give some background, Tegra194's PCIe
On 12/04/2021 14:34, liuqi (BA) wrote:
Hi John,
Thanks for reviewing this.
On 2021/4/9 18:22, John Garry wrote:
On 09/04/2021 10:05, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device
Hi
I'm starting this mail to seek advice on the best approach to be taken
to add support for the driver of the PCIe root port's DMA engine.
To give some background, Tegra194's PCIe IPs are dual-mode PCIe IPs i.e.
they work either in the root port mode or in the endpoint mode based on
the boot
From: Ben Peled
Add system controller and reset bit to each pcie to enable pcie mac reset
Signed-off-by: Ben Peled
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts
Hi John,
Thanks for reviewing this.
On 2021/4/9 18:22, John Garry wrote:
On 09/04/2021 10:05, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple Root Ports, and each
and seems to work
just fine OOTB.
PCIe IDs taken from:
https://github.com/sonyxperiadev/kernel/commit/9e43fefbac8e43c3d7792e73ca52a052dd86d7e3.patch
I don't see 4359 firmware in linux-firmware repo so what are you using?
Regards,
Arend
Hi Arend,
we are using firmwares that come with our
Fixes: ed0022da8bd9 ("iwlwifi: pcie: set LTR on more devices")
Signed-off-by: Luca Coelho
Signed-off-by: Kalle Valo
Link:
https://lore.kernel.org/r/iwlwifi.20210326125611.675486178ed1.Ib61463aba6920645059e366dcdca4c4c77f0ff58@changeid
Signed-off-by: Greg Kroah-Hartman
---
drivers/ne
Fixes: ed0022da8bd9 ("iwlwifi: pcie: set LTR on more devices")
Signed-off-by: Luca Coelho
Signed-off-by: Kalle Valo
Link:
https://lore.kernel.org/r/iwlwifi.20210326125611.675486178ed1.Ib61463aba6920645059e366dcdca4c4c77f0ff58@changeid
Signed-off-by: Greg Kroah-Hartman
---
drivers/ne
On 07-03-2021 12:35, Konrad Dybcio wrote:
Add support for BCM43596 dual-band AC chip, found in
SONY Xperia X Performance, XZ and XZs smartphones (and
*possibly* other devices from other manufacturers).
The chip doesn't require any special handling and seems to work
just fine OOTB.
PCIe IDs
Lorenzo Pieralisi 於 2021年4月9日 週五 下午4:54寫道：
>
> On Tue, 6 Apr 2021 17:26:28 +0800, Greentime Hu wrote:
> > This patchset includes SiFive FU740 PCIe host controller driver. We also
> > add pcie_aux clock and pcie_power_on_reset controller to prci driver for
>
Fixes: e1181b5bbc3c ("Documentation: misc-devices: Add Documentation for
dw-xdata-pcie driver")
Link:
https://lore.kernel.org/linux-next/20210406214615.40cf3...@canb.auug.org.au/
Reported-by: Stephen Rothwell
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pci
-pcie.rst
+++ b/Documentation/misc-devices/dw-xdata-pcie.rst
@@ -4,37 +4,61 @@
Driver for Synopsys DesignWare PCIe traffic generator (also known as xData)
===
+Supported chips:
+Synopsys DesignWare PCIe prototype solution
: Krzysztof Wilczy??ski
Cc: Stephen Rothwell
Gustavo Pimentel (2):
dw-xdata-pcie: Fix documentation build warns
dw-xdata-pcie: Update outdated info and improve text format
Documentation/misc-devices/dw-xdata-pcie.rst | 76 ++--
Documentation/misc-devices/index.rst
On Wed, Apr 07, 2021 at 10:31:48PM +0200, Gustavo Pimentel wrote:
> Fixes documentation build warnings related to indentation and text
> formatting, such as:
>
> Documentation/misc-devices/dw-xdata-pcie.rst:20: WARNING: Unexpected
> indentation.
> Documentation/misc-devices/dw-xdata-pcie.rst:24:
This adds a new function called by MSI handler in DesignWare PCIe framework,
that invokes PME and AER funcions to detect the factor from SoC-dependent
registers.
Changes since v9:
- Fix the description of pcie_prot_service_get_irq()
Changes since v8:
- Add uniphier_pcie_host_init_complete
Hello,
This query is regarding Function level reset feature for SRIOV.
As per code in Linux PCIe driver the function level reset is done by writing
“1” to “reset” under sysfs interface.
e.g. “echo 1 > /sys/bus/pci/devices/ /reset “
As function level reset is not triggered
On 09/04/2021 10:05, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple Root Ports, and each RCiEP is
registered as a PMU in /sys/bus/event_source/devices, so users can
Edit: Retry, as I did not consider, that my mail-client would make this
party html.
Dear maintainers,
I recently encountered an issue on my Proxmox server system, that
includes a Qualcomm QCA6174 m.2 PCIe wifi module.
https://deviwiki.com/wiki/AIRETOS_AFX-QCA6174-NX
On system boot
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple Root Ports, and each RCiEP is
registered as a PMU in /sys/bus/event_source/devices, so users can
select target PMU, and use filter
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported on
HiSilicon HIP09 platform. Document it to provide guidance on how to
use it.
Signed-off-by: Qi Liu
---
Documentation/admin-guide/perf/hisi-pcie-pmu.rst | 104 +++
1 file changed, 104 insertions
This patchset adds support for HiSilicon PCIe Performance Monitoring
Unit(PMU). It is a PCIe Root Complex integrated End Point(RCiEP) device
added on Hip09. Each PCIe Core has a PMU RCiEP to monitor multi root
ports and all Endpoints downstream these root ports.
HiSilicon PCIe PMU is supported
On Tue, 6 Apr 2021 17:26:28 +0800, Greentime Hu wrote:
> This patchset includes SiFive FU740 PCIe host controller driver. We also
> add pcie_aux clock and pcie_power_on_reset controller to prci driver for
> PCIe driver to use it.
>
> This is tested with e1000e: Intel(R) PRO/1000 Ne
Add PCIe + DP no SSC multilink configuration sequences.
Signed-off-by: Swapnil Jakhade
---
drivers/phy/cadence/phy-cadence-torrent.c | 131 ++
1 file changed, 131 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/phy/cadence/phy-cadence
Lorenzo Pieralisi 於 2021年4月9日 週五 上午12:25寫道：
>
> On Tue, Apr 06, 2021 at 05:26:28PM +0800, Greentime Hu wrote:
> > This patchset includes SiFive FU740 PCIe host controller driver. We also
> > add pcie_aux clock and pcie_power_on_reset controller to prci driver for
>
On Tue, Apr 06, 2021 at 05:26:28PM +0800, Greentime Hu wrote:
> This patchset includes SiFive FU740 PCIe host controller driver. We also
> add pcie_aux clock and pcie_power_on_reset controller to prci driver for
> PCIe driver to use it.
>
> This is tested with e1000e: Intel(R) P
1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic
> using CCI
>
> On Mon, 22 Feb 2021 14:17:31 +0530, Bharat Kumar Gogada wrote:
> > Add support for routing PCIe DMA traffic coherently when Cache
> > Coherent Interconnect (CCI) is enabled in the system.
> > The &qu
On Tue, 06 Apr 2021 17:26:32 +0800, Greentime Hu wrote:
> Add PCIe host controller DT bindings of SiFive FU740.
>
> Signed-off-by: Greentime Hu
> ---
> .../bindings/pci/sifive,fu740-pcie.yaml | 113 ++
> 1 file changed, 113 insertions(+)
>
On Tue, Apr 06, 2021 at 05:26:33PM +0800, Greentime Hu wrote:
> From: Paul Walmsley
>
> Add driver for the SiFive FU740 PCIe host controller.
> This controller is based on the DesignWare PCIe core.
>
> Signed-off-by: Paul Walmsley
> Co-developed-by: Henry Styles
> Sig
Hi John,
On Thu, Apr 08, 2021 at 01:55:02PM +0100, John Garry wrote:
> On 08/04/2021 10:01, Jonathan Cameron wrote:
> > On Wed, 7 Apr 2021 21:40:05 +0100
> > Will Deacon wrote:
> >
> > > On Wed, Apr 07, 2021 at 05:49:02PM +0800, Qi Liu wrote:
> > > >
On 2021/4/7 18:25, Greg KH wrote:
> On Wed, Apr 07, 2021 at 06:03:11PM +0800, Yicong Yang wrote:
>> On 2021/4/6 21:49, Greg KH wrote:
>>> On Tue, Apr 06, 2021 at 08:45:50PM +0800, Yicong Yang wrote:
>>>> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Co
On 08/04/2021 10:01, Jonathan Cameron wrote:
On Wed, 7 Apr 2021 21:40:05 +0100
Will Deacon wrote:
On Wed, Apr 07, 2021 at 05:49:02PM +0800, Qi Liu wrote:
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP
Hi,
Thanks for your review.
On Wed, Apr 07, 2021 at 09:27:34AM -0500, Rob Herring wrote:
> On Wed, Apr 07, 2021 at 12:18:38PM +0900, Nobuhiro Iwamatsu wrote:
> > Add support to PCIe RC controller on Toshiba Visconti ARM SoCs.
> > PCIe controller is based of Synopsys Desig
On Wed, 7 Apr 2021 21:40:05 +0100
Will Deacon wrote:
> On Wed, Apr 07, 2021 at 05:49:02PM +0800, Qi Liu wrote:
> > PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
> > to sample bandwidth, latency, buffer occupation etc.
> >
> > Each PMU RCiEP de
Hi,
Thanks for your review.
On Wed, Apr 07, 2021 at 08:18:58AM -0500, Rob Herring wrote:
> On Tue, Apr 6, 2021 at 10:19 PM Nobuhiro Iwamatsu
> wrote:
> >
> > This commit adds the Device Tree binding documentation that allows
> > to describe the PCIe controller found
On Wed, Apr 07, 2021 at 05:49:02PM +0800, Qi Liu wrote:
> PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
> to sample bandwidth, latency, buffer occupation etc.
>
> Each PMU RCiEP device monitors multiple root ports, and each RCiEP is
> registered as a
With the recent addition of dw-xdata-pcie, the documentation build now
warns about a missing reference on the table of content related to it.
This fix solves the following error:
Documentation/misc-devices/dw-xdata-pcie.rst: WARNING: document isn't
included in any toctree
Fixes: e1181b5bbc3c
Kroah-Hartman
Cc: Jonathan Corbet
Cc: Bjorn Helgaas
Cc: Krzysztof Wilczy??ski
Cc: Stephen Rothwell
Gustavo Pimentel (2):
dw-xdata-pcie: Fix documentation build warns and update outdated info
misc-device: Add dw-xdata-pcie to toctree(index)
Documentation/misc-devices/dw-xdata-pcie.rst | 62
xdata-pcie driver")
Link:
https://lore.kernel.org/linux-next/20210406214615.40cf3...@canb.auug.org.au/
Reported-by: Stephen Rothwell
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/dw-xdata-pcie.rst | 62 +++-
1 file changed, 43 insertions(+), 19
On Mon, 22 Feb 2021 14:17:31 +0530, Bharat Kumar Gogada wrote:
> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or
On Wed, Apr 07, 2021 at 12:18:38PM +0900, Nobuhiro Iwamatsu wrote:
> Add support to PCIe RC controller on Toshiba Visconti ARM SoCs.
> PCIe controller is based of Synopsys DesignWare PCIe core.
>
> Signed-off-by: Yuji Ishikawa
> Signed-off-by: Nobuhiro Iwamatsu
> ---
> d
' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Qi-Liu/drivers-perf-hisi-Add-support-for-PCIe-PMU/20210407-175356
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
2d743660786ec51f5c1fefd5782bbdee7b227db0
config
On Tue, Apr 6, 2021 at 10:19 PM Nobuhiro Iwamatsu
wrote:
>
> This commit adds the Device Tree binding documentation that allows
> to describe the PCIe controller found in Toshiba Visconti SoCs.
>
> Signed-off-by: Nobuhiro Iwamatsu
> ---
> .../bindings/pci/toshiba,visco
Currently all PCIE windows point to bus address 0x0, which does not match
the values obtained from hardware during EA.
Replace those values with CPU addresses, since in reality we
have a 1:1 mapping between the two.
Signed-off-by: Kornel Duleba
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
On Wed, Apr 07, 2021 at 06:03:11PM +0800, Yicong Yang wrote:
> On 2021/4/6 21:49, Greg KH wrote:
> > On Tue, Apr 06, 2021 at 08:45:50PM +0800, Yicong Yang wrote:
> >> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex
> >> integrated Endpoint(RCiEP) devic
On 2021/4/6 21:49, Greg KH wrote:
> On Tue, Apr 06, 2021 at 08:45:50PM +0800, Yicong Yang wrote:
>> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex
>> integrated Endpoint(RCiEP) device, providing the capability
>> to dynamically monitor and tune
This patchset adds support for HiSilicon PCIe Performance Monitoring
Unit(PMU). It is a PCIe Root Complex integrated End Point(RCiEP) device
added on Hip09. Each PCIe Core has a PMU RCiEP to monitor multi root
ports and all Endpoints downstream these root ports.
HiSilicon PCIe PMU is supported
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported
to sample bandwidth, latency, buffer occupation etc.
Each PMU RCiEP device monitors multiple root ports, and each RCiEP is
registered as a pmu in /sys/bus/event_source/devices, so users can
select target PMU, and use filter
PCIe PMU Root Complex Integrated End Point(RCiEP) device is supported on
HiSilicon HIP09 platform, and document it to provide guidance on how to
use it.
Reviewed-by: John Garry
Signed-off-by: Qi Liu
---
Documentation/admin-guide/perf/hisi-pcie-pmu.rst | 103 +++
1 file
This commit adds the Device Tree binding documentation that allows
to describe the PCIe controller found in Toshiba Visconti SoCs.
Signed-off-by: Nobuhiro Iwamatsu
---
.../bindings/pci/toshiba,visconti-pcie.yaml | 121 ++
1 file changed, 121 insertions(+)
create mode 100644
Hi,
This series is the PCIe driver for Toshiba's ARM SoC, Visconti[0].
This provides DT binding documentation, device driver, MAINTAINER files.
Best regards,
Nobuhiro
[0]:
https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recognition-processors-visconti.html
Nobuhiro
Add support to PCIe RC controller on Toshiba Visconti ARM SoCs.
PCIe controller is based of Synopsys DesignWare PCIe core.
Signed-off-by: Yuji Ishikawa
Signed-off-by: Nobuhiro Iwamatsu
---
drivers/pci/controller/dwc/Kconfig | 10 +
drivers/pci/controller/dwc/Makefile| 1
Add entries for Toshiba Visconti PCIe controller binding and driver.
Signed-off-by: Nobuhiro Iwamatsu
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8a154939ae27..3e5187c5b8d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2621,11 +2621,13
From: Hou Zhiqiang
The LS1043A PCIe controller has some control registers
in SCFG block, so add the SCFG phandle for each PCIe
controller DT node.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff
From: Hou Zhiqiang
Add the big-endian property for LS1012A, LS1043A and LS1046A
PCIe devicetree nodes.
Signed-off-by: Hou Zhiqiang
---
V5:
- No change
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 +
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
arch/arm64/boot/dts/freescale
in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Yicong-Yang/Add-support-for-HiSilicon-PCIe-Tune-and-Trace-device/20210406-204959
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
0a50438c84363bd37fe18fe432888ae9a074dcab
config
Add missing entry on the table of content related to dw-xdata-pcie misc
driver reported in a warning by doing *make htmldocs*.
Fixes: e1181b5bbc3c ("Documentation: misc-devices: Add Documentation for
dw-xdata-pcie driver")
Link:
https://lore.kernel.org/linux-next/2021040621
On Tue, Apr 6, 2021 at 9:20 AM Lorenzo Pieralisi
wrote:
>
> [+ Rob, Robin]
>
> On Mon, Feb 22, 2021 at 02:17:31PM +0530, Bharat Kumar Gogada wrote:
> > Add support for routing PCIe DMA traffic coherently when
> > Cache Coherent Interconnect (CCI) is enabled in the syste
On Tue, Apr 06, 2021 at 08:07:43PM +0200, Gustavo Pimentel wrote:
> Add missing entry on the table of content related to dw-xdata-pcie misc
> driver reported in a warning by doing *make htmldocs*.
>
> Signed-off-by: Gustavo Pimentel
> ---
> Documentation/misc-devices/index.r
Add missing entry on the table of content related to dw-xdata-pcie misc
driver reported in a warning by doing *make htmldocs*.
Signed-off-by: Gustavo Pimentel
---
Documentation/misc-devices/index.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/misc-devices/index.rst
b
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