Re: [EXT] [PATCH v6 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

On 21/02/19 4:11 PM, Bean Huo (beanhuo) wrote: > Hi, Vignesh > >> >> Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an >> integrated PHY. IP register layout is very similar to existing QSPI IP >> except for >> additional bits to support Octal and Octal DDR mode. Theref

Re: [EXT] [PATCH v6 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

On Thu, 21 Feb 2019 10:41:33 + "Bean Huo (beanhuo)" wrote: > Hi, Vignesh > > > > >Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an > >integrated PHY. IP register layout is very similar to existing QSPI IP > >except for > >additional bits to support Octal and Octal

RE: [EXT] [PATCH v6 2/2] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

Hi, Vignesh > >Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an >integrated PHY. IP register layout is very similar to existing QSPI IP except >for >additional bits to support Octal and Octal DDR mode. Therefore, extend >current driver to support Octal mode. Only Octal S