xilinx.com>
> > Cc: Arnd Bergmann <a...@arndb.de>; Greg Kroah-Hartman
> > <gre...@linuxfoundation.org>; LKML <linux-kernel@vger.kernel.org>;
> > michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval
> > Rajeshbhai Shah <ds...@xilinx.com>
> >
: Arnd Bergmann ; Greg Kroah-Hartman
> > ; LKML ;
> > michal.si...@xilinx.com; Hyun Kwon ; Dhaval
> > Rajeshbhai Shah
> > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> > logicoreIP init driver
> >
> > Daval,
> >
> > On Tue, Dec
undation.org>; LKML <linux-kernel@vger.kernel.org>;
> michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval
> Rajeshbhai Shah <ds...@xilinx.com>
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> Daval,
>
>
bhai Shah
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> Daval,
>
> On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah
> wrote:
> > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> > cr
Daval,
On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
>
>
Daval,
On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
>
> Signed-off-by: Dhaval Shah
[]
>
.@xilinx.com>
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote:
> > > Then you need to explain this a lot better, posting a random driver
> > &g
nux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote:
> > > Then you need to explain this a lot better, posting a random driver
> > > for submission that is expected to be used by
On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote:
> > Then you need to explain this a lot better, posting a random driver for
> > submission that is expected to be used by another one isn't ok.
> > Post the whole patch series please, we do not add infrastructure to the
> >
On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote:
> > Then you need to explain this a lot better, posting a random driver for
> > submission that is expected to be used by another one isn't ok.
> > Post the whole patch series please, we do not add infrastructure to the
> >
.@xilinx.com>
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote:
> > Hi Greg k-h,
> >
> > Thanks a lot for the review.
> >
> > Replie
nux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote:
> > Hi Greg k-h,
> >
> > Thanks a lot for the review.
> >
> > Replies inline.
>
> As they should be, perhaps
On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote:
> Hi Greg k-h,
>
> Thanks a lot for the review.
>
> Replies inline.
As they should be, perhaps you need a better email client :)
>
> > +config XILINX_VCU
> > + tristate "Xilinx VCU Init"
> > + default n
>
>
On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote:
> Hi Greg k-h,
>
> Thanks a lot for the review.
>
> Replies inline.
As they should be, perhaps you need a better email client :)
>
> > +config XILINX_VCU
> > + tristate "Xilinx VCU Init"
> > + default n
>
>
nx.com; Hyun
Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com>
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP
init driver
On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the
; Dhaval Rajeshbhai Shah
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP
init driver
On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api whi
Mailing List
<linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun
Kwon <hy...@xilinx.com>
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP
init driver
On Tue, Dec 5, 2017 at 1:38 PM, Dhaval Rajeshbhai Shah <ds...@xil
l Rajeshbhai Shah
> Cc: gregkh ; Linux Kernel Mailing List
> ; Michal Simek
> ; Hyun Kwon ; Dhaval
> Rajeshbhai Shah
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wro
om>
> Cc: gregkh <gre...@linuxfoundation.org>; Linux Kernel Mailing List
> <linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun
> Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com>
> Subject: Re: [PATCH] [linux][master][v1] misc:
ichal Simek ; Hyun
> Kwon ; Dhaval Rajeshbhai Shah
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
>
> On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
>> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
>&
On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
Your subject has a lot of [] in it,
On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
Your subject has a lot of [] in it,
ation.org>; Linux Kernel Mailing List
<linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun
Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com>
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP
init dri
; Hyun
Kwon ; Dhaval Rajeshbhai Shah
Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP
init driver
On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide t
On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
>
> Signed-off-by:
On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote:
> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design
> created. This driver will provide the api which can be used
> by the encoder and decoder driver to get the configured value.
>
> Signed-off-by: Dhaval Shah
Can you explain
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