On Tue, Apr 08, 2014 at 07:07:40PM +0800, Nicolin Chen wrote:
> Sir, I can't find this patch on any of the remote branches: for-next,
> topic/fsl-sai and fix/fsl-sai. Where could I find it?
It's in the fix branch.
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On Fri, Apr 04, 2014 at 11:05:32AM +0100, Mark Brown wrote:
> On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> > The BCP bit in TCR4/RCR4 register rules as followings:
> > 0 Bit clock is active high with drive outputs on rising edge
> > and sample inputs on falling edge.
> >
On Fri, Apr 04, 2014 at 03:09:47PM +0800, Nicolin Chen wrote:
> The BCP bit in TCR4/RCR4 register rules as followings:
> 0 Bit clock is active high with drive outputs on rising edge
> and sample inputs on falling edge.
> 1 Bit clock is active low with drive outputs on falling edge
> and
>
> Is that possible for you to test those two clock patches for fsl_sai?
>
> I think most of us are waiting for your reply to it. And I'd really
> like to move on to append clock dividing code into the driver so both
> of vybrid and imx can easily enable the DAI master mode.
>
Certainly, I wi
Hi Xiubo,
On Fri, Apr 04, 2014 at 03:37:00PM +0800, Xiubo Li-B47053 wrote:
>
> > Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
> >
> > The BCP bit in TCR4/RCR4 register rules as followings:
> > 0 Bit clock is active high with drive outputs on rising edge
> > and sam
> Subject: [PATCH] ASoC: fsl_sai: Fix Bit Clock Polarity configurations
>
> The BCP bit in TCR4/RCR4 register rules as followings:
> 0 Bit clock is active high with drive outputs on rising edge
> and sample inputs on falling edge.
> 1 Bit clock is active low with drive outputs on falling
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