Hi Felipe,
On Monday, June 24, 2019 13:58, Felipe Balbi wrote:
>
> Hi,
>
> Ran Wang writes:
> >> >> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
> >> >> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n)((n) & 0x1f)
> >> >> > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n
Hi,
Ran Wang writes:
>> >> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
>> >> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
>> >> > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
>> >> > >> >> > @@ -859,6 +867,7 @@ struct dwc3_scratchp
Hi Felipe,
On Monday, June 17, 2019 20:53, Felipe Balbi wrote:
> Hi,
>
> Ran Wang writes:
> > Hi Felipe,
> >
> > On Thursday, May 30, 2019 17:09, Ran Wang wrote:
> >>
> >>
> >> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
> >> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n)
Hi,
Ran Wang writes:
> Hi Felipe,
>
> On Thursday, May 30, 2019 17:09, Ran Wang wrote:
>>
>>
>> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
>> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
>> > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n)(((n) << 5) & 0
Hi Felipe,
On Thursday, May 30, 2019 17:09, Ran Wang wrote:
>
>
> > >> >> > /* Global Debug Queue/FIFO Space Available Register */
> > >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
> > >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
> > >> >> > @@ -859,6 +867,7 @@ st
Hi Felipe,
On Tuesday, May 28, 2019 18:20, Felipe Balbi wrote:
>
> >> >> > /* Global Debug Queue/FIFO Space Available Register */
> >> >> > #define DWC3_GDBGFIFOSPACE_NUM(n)((n) & 0x1f)
> >> >> > #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
> >> >> > @@ -859,6 +867,7 @@ struc
Hi Felipe,
On Wednesday, May 29, 2019 18:25, Felipe Balbi wrote:
>
> Hi,
>
> Ran Wang writes:
> >> >> >> c) WHAT does this mean for PCI devices?
> >
> > According to DWC3 data book, I think this (PCI) mean to the case of 'master
> bus type = Native'
> > The data book describes this feature as '
Hi,
Ran Wang writes:
>> >> >> c) WHAT does this mean for PCI devices?
>
> According to DWC3 data book, I think this (PCI) mean to the case of 'master
> bus type = Native'
> The data book describes this feature as 'system bus DMA option for the master
> bus,
> which may be configured as AHB, A
HI Felipe,
On Tuesday, May 28, 2019 18:20, Felipe Balbi wrote:
>
> Hi,
>
> Ran Wang writes:
>
> > Hi Felipe,
> >
> > Sorry for the late reply:
> >
> > On Wednesday, November 15, 2017 18:23, Felipe Balbi wrote:
>
> that's 1.5 year ago. I really don't remember the details of this conversati
Hi,
Ran Wang writes:
> Hi Felipe,
>
> Sorry for the late reply:
>
> On Wednesday, November 15, 2017 18:23, Felipe Balbi wrote:
that's 1.5 year ago. I really don't remember the details of this conversation
>> Ran Wang writes:
>> >> Ran Wang writes:
>> >> > Add support for USB3 snooping
Hi Felipe,
Sorry for the late reply:
On Wednesday, November 15, 2017 18:23, Felipe Balbi wrote:
>
> Hi,
>
> Ran Wang writes:
> >> Ran Wang writes:
> >> > Add support for USB3 snooping by asserting bits in register
> >> > DWC3_GSBUSCFG0 for data and descriptor.
> >>
> >> we know *how* to e
Hi,
Ran Wang writes:
>> Ran Wang writes:
>> > Add support for USB3 snooping by asserting bits in register
>> > DWC3_GSBUSCFG0 for data and descriptor.
>>
>> we know *how* to enable a feature :-) It's always the same, you fiddle with
>> some registers and it works. What you failed to tell us is
Ran
> Wang ; Rob Herring ;
> devicet...@vger.kernel.org
> Subject: Re: [PATCH] usb: dwc3: Enable the USB snooping
>
>
> Hi,
>
> Ran Wang writes:
> > Add support for USB3 snooping by asserting bits in register
> > DWC3_GSBUSCFG0 for data and descriptor.
>
Hi,
Ran Wang writes:
> Add support for USB3 snooping by asserting bits
> in register DWC3_GSBUSCFG0 for data and descriptor.
we know *how* to enable a feature :-) It's always the same, you fiddle
with some registers and it works. What you failed to tell us is:
a) WHY do you need this?
b) WHY d
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