el.org; Linux ARM
>
> Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
>
>
>
> On Fri, 22 Jan 2021, at 18:45, Ryan Chen wrote:
> > Hello,
> > How about this patch progress?
> > It does impact a lot of machine that when BMC b
Cc: Andrew Jeffery ; Michael Turquette
> > ; Ryan Chen ;
> > BMC-SW ; Linux ARM
> > ; linux-aspeed
> > ; linux-...@vger.kernel.org; Linux Kernel
> > Mailing List
> > Subject: Re: Re: [PATCH 1/1] clk: aspeed: modify some default clks are
> > critical
> &g
: Re: Re: [PATCH 1/1] clk: aspeed: modify some default clks are
> critical
>
> Stephen,
>
> On 10/14/20 12:16 PM, Stephen Boyd wrote:
> > Quoting Joel Stanley (2020-10-13 22:28:00)
> >> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> >>>
> >>
Stephen,
On 10/14/20 12:16 PM, Stephen Boyd wrote:
> Quoting Joel Stanley (2020-10-13 22:28:00)
>> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
>>>
>>> Quoting Ryan Chen (2020-09-28 00:01:08)
In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
default for Host S
Thanks for the response Stephen. Sorry it's taken me a while to get back to you.
On Wed, 14 Oct 2020 at 17:16, Stephen Boyd wrote:
>
> Quoting Joel Stanley (2020-10-13 22:28:00)
> > On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> > >
> > > Quoting Ryan Chen (2020-09-28 00:01:08)
> > > > In A
Quoting Joel Stanley (2020-10-13 22:28:00)
> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> >
> > Quoting Ryan Chen (2020-09-28 00:01:08)
> > > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> > > default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
>
> Quoting Ryan Chen (2020-09-28 00:01:08)
> > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> > default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> > eSPI slave channel, those clks can't be disable
ist
> Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
>
> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd wrote:
> >
> > Quoting Ryan Chen (2020-09-28 00:01:08)
> > > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2
> >
Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side access
Hyun Yoo
> > > ; Andrew Jeffery
> > > Cc: Michael Turquette ; Stephen Boyd
> > > ; linux-...@vger.kernel.org; Linux ARM
> > > ; linux-aspeed
> > > ; Linux Kernel Mailing List
> > > ; BMC-SW
> > > Subject: Re: [PATCH 1/1] clk: aspeed: m
M
> > ; linux-aspeed
> > ; Linux Kernel Mailing List
> > ; BMC-SW
> > Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
> >
> > On Mon, 28 Sep 2020 at 07:01, Ryan Chen
> > wrote:
> > >
> > > In ASPEED SoC LCLK is
t: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical
>
> On Mon, 28 Sep 2020 at 07:01, Ryan Chen
> wrote:
> >
> > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2
> > are default for Host SuperIO UART device, eSPI clk for Host eSPI bus
&
On Mon, 28 Sep 2020 at 07:01, Ryan Chen wrote:
>
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host s
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