On Wed, Apr 10, 2019 at 07:41:47PM +, Ghannam, Yazen wrote:
> So I'm thinking to add another patch to the set. This will set
> mce_bank.init=0 if we read MCA_CTL=0 from the hardware.
Ok.
> Then we check if mce_bank.init=0 in the set/show functions and give a
> message if the bank is not used.
> Subject: Re: [PATCH RESEND 2/5] x86/MCE: Handle MCA controls in a per_cpu way
>
> On Wed, Apr 10, 2019 at 04:58:12PM +, Ghannam, Yazen wrote:
> > Yes, unused banks in the middle are counted in the MCG_CAP[Count] value.
>
> Good.
>
> > Okay, so you're saying th
On Wed, Apr 10, 2019 at 04:58:12PM +, Ghannam, Yazen wrote:
> Yes, unused banks in the middle are counted in the MCG_CAP[Count] value.
Good.
> Okay, so you're saying the sysfs access should fail if a bank is
> disabled. Is that correct?
Well, think about it. If a bank is not operational for
> -Original Message-
> From: Borislav Petkov
> Sent: Wednesday, April 10, 2019 11:41 AM
> To: Ghannam, Yazen
> Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org;
> tony.l...@intel.com; x...@kernel.org
> Subject: Re: [PATCH RESEND 2/5] x86/MCE: Handle MCA
On Wed, Apr 10, 2019 at 04:36:30PM +, Ghannam, Yazen wrote:
> We have this case on AMD Family 17h with Bank 4. The hardware enforces
> this bank to be Read-as-Zero/Writes-Ignored.
>
> This behavior is enforced whether the bank is in the middle or at the
> end.
Does num_banks contain the disabl
> -Original Message-
> From: Borislav Petkov
> Sent: Tuesday, April 9, 2019 3:34 PM
> To: Ghannam, Yazen
> Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org;
> tony.l...@intel.com; x...@kernel.org
> Subject: Re: [PATCH RESEND 2/5] x86/MCE: Handle MCA cont
On Mon, Apr 08, 2019 at 06:55:59PM +, Ghannam, Yazen wrote:
> We already have the case where some banks are not initialized either
> due to quirks or because they are Read-as-Zero, but we don't try to
> skip creating their files. With this full set (see patch 5), an unused
> bank will return a
> -Original Message-
> From: Borislav Petkov
> Sent: Monday, April 8, 2019 12:52 PM
> To: Ghannam, Yazen
> Cc: linux-e...@vger.kernel.org; linux-kernel@vger.kernel.org;
> tony.l...@intel.com; x...@kernel.org
> Subject: Re: [PATCH RESEND 2/5] x86/MCE: Handle MCA cont
On Mon, Apr 08, 2019 at 02:12:16PM +, Ghannam, Yazen wrote:
> From: Yazen Ghannam
>
> Current AMD systems have unique MCA banks per logical CPU even though
> the type of the banks may all align to the same bank number. Each CPU
> will have control of a set of MCA banks in the hardware and the
9 matches
Mail list logo
