> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Tuesday, October 23, 2018 6:17 AM
[...]
>
> On Sun, Oct 21, 2018 at 01:11:09PM +, A.s. Dong wrote:
> > i.MX7ULP Clock functions are under joint control of the System Clock
> > Generation (SCG) modules, Peripheral
On Sun, Oct 21, 2018 at 01:11:09PM +, A.s. Dong wrote:
> i.MX7ULP Clock functions are under joint control of the System
> Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
> modules, and Core Mode Controller (CMC)1 blocks
>
> Note IMX7ULP has two clock domains: M4 and A7. This bin
On Fri, May 25, 2018 at 03:51:08PM +0800, Dong Aisheng wrote:
> i.MX7ULP Clock functions are under joint control of the System
> Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
> modules, and Core Mode Controller (CMC)1 blocks
>
> Note IMX7ULP has two clock domains: M4 and A7. This
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