Hi Stephen,
> Subject: Re: [PATCH V2 1/4] clk: imx: pll14xx: avoid glitch when set rate
>
> Quoting Peng Fan (2019-08-26 02:42:14)
> > From: Peng Fan
> >
> > According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB
> > is changed from 0 to 1
Quoting Peng Fan (2019-08-26 02:42:14)
> From: Peng Fan
>
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
>
> So set BYPASS when
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