Re: [PATCH v2 2/4] phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support

Hi, On Tuesday 07 October 2014 03:49 PM, Vivek Gautam wrote: > Exynos7 SoC has now separate gate control for 125MHz pipe3 phy > clock, as well as 60MHz utmi phy clock. > So get the same and control in the phy-exynos5-usbdrd driver. > > Signed-off-by: Vivek Gautam > --- > .../devicetree/bindings

RE: [PATCH v2 2/4] phy: exynos5-usbdrd: Add pipe-clk and utmi-clk support

Hi Vivek, > Exynos7 SoC has now separate gate control for 125MHz pipe3 phy > clock, as well as 60MHz utmi phy clock. > So get the same and control in the phy-exynos5-usbdrd driver. In case of the PHY the situation is pretty much the same as with DWC3 core. Here we should control 6 clocks to make