Hi Shawn,
[...]
> > + DCFG_CCSR_DEVDISR1,
> > + ls1021a_clk_shift(0));
>
> I think we can ignore the 80 columns warning and put these on one line
> to make the code a bit easier to read.
>
Yes, it looks better,
> > > As the parent of the clocks registered by this function is "dummy" from
> > > what I see, what is the point of setting flag CLK_SET_RATE_PARENT then?
> > >
> > > > + CLK_IGNORE_UNUSED, reg, shift,
> > >
> > > Why flag CLK_IGNORE_UNUSED?
> > >
> >
> > As the SoC reference
On Thu, Sep 25, 2014 at 05:22:29PM +0800, Xiubo Li-B47053 wrote:
...
> > > + clks[LS1021A_CLK_FLEXTIMER1_EN] = ls1021a_clk_gate("flextimer1_en",
> > > + "dummy", DCFG_CCSR_DEVDISR5,
> > > + ls1021a_clk_shift(31));
> >
Hi,
[...]
> > +Required properties:
> > +- compatible: Should be "fsl,ls1021a-gate"
> > +- reg: Address and length of the register set
> > +- #clock-cells:Should be <1>
> > +
> > +Optional property:
> > +- big-endian: If present the gate cl
On Tue, Sep 23, 2014 at 08:44:35PM +0800, Xiubo Li wrote:
> A given application may not use all the peripherals on the device.
> In this case, it may be desirable to disable unused peripherals.
> DCFG provides a mechanism for gating clocks to IP blocks that are
> not used when running an applicatio
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