Thanks Lorenzo.
> -Original Message-
> From: Lorenzo Pieralisi
> Sent: Wednesday, April 7, 2021 9:32 PM
> To: linux-...@vger.kernel.org; Bharat Kumar Gogada ;
> linux-kernel@vger.kernel.org
> Cc: lorenzo.pieral...@arm.com; bhelg...@google.com
> Subject: Re: [PATCH v3
On Mon, 22 Feb 2021 14:17:31 +0530, Bharat Kumar Gogada wrote:
> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or not.
> Refer to https://developer.arm.com
On Tue, Apr 6, 2021 at 9:20 AM Lorenzo Pieralisi
wrote:
>
> [+ Rob, Robin]
>
> On Mon, Feb 22, 2021 at 02:17:31PM +0530, Bharat Kumar Gogada wrote:
> > Add support for routing PCIe DMA traffic coherently when
> > Cache Coherent Interconnect (CCI) is enabled in the system.
> > The "dma-coherent" pr
[+ Rob, Robin]
On Mon, Feb 22, 2021 at 02:17:31PM +0530, Bharat Kumar Gogada wrote:
> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or not.
> Refer to htt
...@vger.kernel.org; linux-kernel@vger.kernel.org
> > Cc: bhelg...@google.com
> > Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA
> > traffic using CCI
> >
> > Ping.
> >
> > > -Original Message-
> > > From:
Ping.
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Monday, March 15, 2021 11:43 AM
> To: Bharat Kumar Gogada ; linux-
> p...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com
> Subject: RE: [PATCH v3 1/2] PCI: xilinx-nwl: Enable cohe
Ping.
> -Original Message-
> From: Bharat Kumar Gogada
> Sent: Monday, February 22, 2021 2:18 PM
> To: linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: bhelg...@google.com; Bharat Kumar Gogada
> Subject: [PATCH v3 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic
> usin
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