On Tue, Jun 16, 2020 at 06:20:19PM -0500, Bjorn Helgaas wrote:
> On Mon, Jun 15, 2020 at 11:15:52AM +0100, Shiju Jose wrote:
> > From: Yicong Yang
> > + if (!guid_equal((guid_t *)gdata->section_type, &hisi_pcie_sec_type) ||
> > + error_data->socket_id != socket)
> > + return NOT
On Mon, Jun 15, 2020 at 11:15:52AM +0100, Shiju Jose wrote:
> From: Yicong Yang
>
> The HiSilicon HIP PCIe controller is capable of handling errors
> on root port and perform port reset separately at each root port.
>
> Add error handling driver for HIP PCIe controller to log
> and report recove
ames.mo...@arm.com; l...@kernel.org; tony.l...@intel.com;
>dan.carpen...@oracle.com; zhangligu...@linux.alibaba.com; Wangkefeng
>(OS Kernel Lab) ; jroe...@suse.de;
>yangyicong ; Jonathan Cameron
>; tanxiaofei ;
>Linuxarm
>Subject: Re: [PATCH v9 2/2] PCI: hip: Add handling of HiSi
On Tue, Jun 16, 2020 at 11:55:46AM +, Shiju Jose wrote:
> >From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
> >ow...@vger.kernel.org] On Behalf Of Andy Shevchenko
> >On Tue, Jun 16, 2020 at 09:12:56AM +, Shiju Jose wrote:
> >> >From: Andy Shevchenko [mailto:andriy.shevche...@linux
le.com; zhangligu...@linux.alibaba.com; Wangkefeng
>> >(OS Kernel Lab) ; jroe...@suse.de;
>> >yangyicong ; Jonathan Cameron
>> >; tanxiaofei
>> >Subject: Re: [PATCH v9 2/2] PCI: hip: Add handling of HiSilicon HIP
>> >PCIe controller errors
>> >
&g
ron
> >; tanxiaofei
> >Subject: Re: [PATCH v9 2/2] PCI: hip: Add handling of HiSilicon HIP PCIe
> >controller errors
> >
> >On Mon, Jun 15, 2020 at 11:15:52AM +0100, Shiju Jose wrote:
...
> >bits.h ?
>
> Ok. I think bits.h was already included throu
.@rjwysocki.net; b...@alien8.de;
>james.mo...@arm.com; l...@kernel.org; tony.l...@intel.com;
>dan.carpen...@oracle.com; zhangligu...@linux.alibaba.com; Wangkefeng
>(OS Kernel Lab) ; jroe...@suse.de;
>yangyicong ; Jonathan Cameron
>; tanxiaofei
>Subject: Re: [PATCH v9 2/2] PCI: hip
On Mon, Jun 15, 2020 at 11:15:52AM +0100, Shiju Jose wrote:
> From: Yicong Yang
>
> The HiSilicon HIP PCIe controller is capable of handling errors
> on root port and perform port reset separately at each root port.
>
> Add error handling driver for HIP PCIe controller to log
> and report recove
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