Re: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-12 Thread Wolfram Sang
On Tue, Mar 11, 2014 at 07:33:45PM +0800, Chew Chiau Ee wrote: > From: Chew, Chiau Ee > > On Intel BayTrail, there was case whereby the resulting fast mode > bus speed becomes slower (~20% slower compared to expected speed) > if using the HCNT/LCNT calculated in the core layer. Thus, this > patch

Re: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-11 Thread Mika Westerberg
On Tue, Mar 11, 2014 at 07:33:45PM +0800, Chew Chiau Ee wrote: > From: Chew, Chiau Ee > > On Intel BayTrail, there was case whereby the resulting fast mode > bus speed becomes slower (~20% slower compared to expected speed) > if using the HCNT/LCNT calculated in the core layer. Thus, this > patch

RE: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value

2014-03-10 Thread Chew, Chiau Ee
> Subject: [PATCHv2 RESEND] i2c: designware-pci: set ideal HCNT, LCNT and SDA > hold time value > > From: Chew, Chiau Ee > > On Intel BayTrail, there was case whereby the resulting fast mode bus speed > becomes slower (~20% slower compared to expected speed) if using the > HCNT/LCNT calculated