On Tue, Jan 19, 2021 at 10:04:23AM +, Shiju Jose wrote:
> This EDAC code for the cache errors is architecture independent for the
> firmware-first error reporting and could be used for other architectures,
I'm not so sure about that because you're lumping all the cache
hierarchies together a
ony.l...@intel.com; r...@rjwysocki.net;
>l...@kernel.org; rrich...@marvell.com; Jonathan Cameron
>; tanxiaofei ;
>linux...@openeuler.org
>Subject: Re: [RFC PATCH 1/2] EDAC/ghes: Add EDAC device for the CPU
>caches
>
>On Fri, Jan 15, 2021 at 11:06:30AM +, Shiju Jose wrote:
On Fri, Jan 15, 2021 at 11:06:30AM +, Shiju Jose wrote:
> L2 cache corrected errors are detected occasionally on few of
> our ARM64 hardware boards. Though it is rare, the probability of
> the CPU cache errors frequently occurring can't be avoided.
> The earlier failure detection by monitoring
ames.mo...@arm.com;
>mchehab+hua...@kernel.org; tony.l...@intel.com; r...@rjwysocki.net;
>l...@kernel.org; rrich...@marvell.com; Linuxarm ;
>xuwei (O) ; Jonathan Cameron
>; John Garry ;
>tanxiaofei ; Shameerali Kolothum Thodi
>; Salil Mehta
>
>Subject: Re: [RFC PATCH 1/2] EDAC
On Tue, Dec 08, 2020 at 05:29:58PM +, Shiju Jose wrote:
> The corrected error count on the CPU caches required
> reporting to the user-space for the predictive failure
> analysis. For this purpose, add an EDAC device and device
> blocks for the CPU caches found.
> The cache's corrected error co
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