On February 20, 2017 2:02:53 PM PST, Paolo Bonzini wrote:
>
>> > Yes. But 150-200 clock cycles are nothing compared to the cache
>misses
>> > you get from preemption, so I'd ignore that. Saving 300 clock
>cycles on
>> > userspace exits from TR+GSBASE would be about 5% on my
On February 20, 2017 2:02:53 PM PST, Paolo Bonzini wrote:
>
>> > Yes. But 150-200 clock cycles are nothing compared to the cache
>misses
>> > you get from preemption, so I'd ignore that. Saving 300 clock
>cycles on
>> > userspace exits from TR+GSBASE would be about 5% on my Haswell.
>>
>>
> > Yes. But 150-200 clock cycles are nothing compared to the cache misses
> > you get from preemption, so I'd ignore that. Saving 300 clock cycles on
> > userspace exits from TR+GSBASE would be about 5% on my Haswell.
>
> That's still 5% :)
Yes, 5% on userspace exits is good (though they're
> > Yes. But 150-200 clock cycles are nothing compared to the cache misses
> > you get from preemption, so I'd ignore that. Saving 300 clock cycles on
> > userspace exits from TR+GSBASE would be about 5% on my Haswell.
>
> That's still 5% :)
Yes, 5% on userspace exits is good (though they're
On Mon, Feb 20, 2017 at 8:51 AM, Paolo Bonzini wrote:
>
>
> On 20/02/2017 17:46, Andy Lutomirski wrote:
>> On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 18/02/2017 04:29, Andy Lutomirski wrote:
There's no code here because the
On Mon, Feb 20, 2017 at 8:51 AM, Paolo Bonzini wrote:
>
>
> On 20/02/2017 17:46, Andy Lutomirski wrote:
>> On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 18/02/2017 04:29, Andy Lutomirski wrote:
There's no code here because the patch is trivial, but I want to run
On 20/02/2017 17:46, Andy Lutomirski wrote:
> On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>>
>>
>> On 18/02/2017 04:29, Andy Lutomirski wrote:
>>> There's no code here because the patch is trivial, but I want to run
>>> the idea by you all first to see if there
On 20/02/2017 17:46, Andy Lutomirski wrote:
> On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>>
>>
>> On 18/02/2017 04:29, Andy Lutomirski wrote:
>>> There's no code here because the patch is trivial, but I want to run
>>> the idea by you all first to see if there are any issues.
>>>
>>>
On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>
>
> On 18/02/2017 04:29, Andy Lutomirski wrote:
>> There's no code here because the patch is trivial, but I want to run
>> the idea by you all first to see if there are any issues.
>>
>> VMX is silly and forces the TSS
On Mon, Feb 20, 2017 at 3:05 AM, Paolo Bonzini wrote:
>
>
> On 18/02/2017 04:29, Andy Lutomirski wrote:
>> There's no code here because the patch is trivial, but I want to run
>> the idea by you all first to see if there are any issues.
>>
>> VMX is silly and forces the TSS limit to the minimum
On 18/02/2017 04:29, Andy Lutomirski wrote:
> There's no code here because the patch is trivial, but I want to run
> the idea by you all first to see if there are any issues.
>
> VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
> wastes lots of cycles bumping it back up to
On 18/02/2017 04:29, Andy Lutomirski wrote:
> There's no code here because the patch is trivial, but I want to run
> the idea by you all first to see if there are any issues.
>
> VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
> wastes lots of cycles bumping it back up to
On 18/02/2017 04:29, Andy Lutomirski wrote:
> There's no code here because the patch is trivial, but I want to run
> the idea by you all first to see if there are any issues.
>
> VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
> wastes lots of cycles bumping it back up to
On 18/02/2017 04:29, Andy Lutomirski wrote:
> There's no code here because the patch is trivial, but I want to run
> the idea by you all first to see if there are any issues.
>
> VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
> wastes lots of cycles bumping it back up to
There's no code here because the patch is trivial, but I want to run
the idea by you all first to see if there are any issues.
VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
wastes lots of cycles bumping it back up to accomodate the io bitmap.
I propose that we rework
There's no code here because the patch is trivial, but I want to run
the idea by you all first to see if there are any issues.
VMX is silly and forces the TSS limit to the minimum on VM exits. KVM
wastes lots of cycles bumping it back up to accomodate the io bitmap.
I propose that we rework
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