On 06/04/13 19:26, Jason Gunthorpe wrote:
On Sun, Dec 09, 2012 at 02:06:48PM +0100, Sebastian Hesselbarth wrote:
The main irq controller will be required for sure, but for the secondary
irq controller we had a discussion long ago. IIRC Gregory proposed to have
shared irqs handled by timer and wa
On Sun, Dec 09, 2012 at 02:06:48PM +0100, Sebastian Hesselbarth wrote:
> The main irq controller will be required for sure, but for the secondary
> irq controller we had a discussion long ago. IIRC Gregory proposed to have
> shared irqs handled by timer and watchdog, I was proposing chained irqs.
On 12/09/2012 09:30 AM, Andrew Lunn wrote:
On Sat, Dec 08, 2012 at 07:57:48PM -0700, Jason Gunthorpe wrote:
On Sat, Dec 08, 2012 at 12:26:24PM +0100, Andrew Lunn wrote:
1) It should have an IRQ domain, like the other IRQ chips we have.
2) It should have a DT binding, like the other IRQ chips w
On Sat, Dec 08, 2012 at 07:57:48PM -0700, Jason Gunthorpe wrote:
> On Sat, Dec 08, 2012 at 12:26:24PM +0100, Andrew Lunn wrote:
>
> > 1) It should have an IRQ domain, like the other IRQ chips we have.
> > 2) It should have a DT binding, like the other IRQ chips we have.
>
> I was going to look a
On Sat, Dec 08, 2012 at 12:26:24PM +0100, Andrew Lunn wrote:
> 1) It should have an IRQ domain, like the other IRQ chips we have.
> 2) It should have a DT binding, like the other IRQ chips we have.
I was going to look at a DT binding for this as a follow on, since
I'll want to bind to these inte
On Fri, Dec 07, 2012 at 03:55:07PM -0700, Jason Gunthorpe wrote:
> The intent of this patch is to expose the other bridge cause
> interrupts to users in the kernel.
>
> - Add orion_bridge_irq_init to create a new edge triggered interrupt
> chip based on the bridge cause register
> - Remove all i
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